History log of /XiangShan/src/main/scala/xiangshan/backend/fu/SRT4Divider.scala (Results 1 – 25 of 25)
Revision Date Author Comments
# e3da8bad 22-Jul-2024 Tang Haojin <[email protected]>

build: purge chisel 3 and add deprecation check (#3250)


# 45f43e6e 19-Jan-2024 Tang Haojin <[email protected]>

chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`


# 8891a219 08-Oct-2023 Yinan Xu <[email protected]>

Bump rocket-chip (#2353)


# 935edac4 21-Sep-2023 Tang Haojin <[email protected]>

chore: remove deprecated brackets, APIs, etc. (#2321)


# 3c02ee8f 25-Dec-2022 wakafa <[email protected]>

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun


# f4b2089a 16-Oct-2021 Yinan Xu <[email protected]>

core: use redirect ports for flush (#1121)

This commit removes flush IO for every module. Flush now re-uses
redirect ports to flush the instructions.


# f7e0356a 08-Oct-2021 Li Qianruo <[email protected]>

Srt16div Bug Fix (#1089)

* Fix a div 1 bug
* Fix a typo


# 9aca92b9 28-Sep-2021 Yinan Xu <[email protected]>

misc: code clean up (#1073)

* rename Roq to Rob

* remove trailing whitespaces

* remove unused parameters


# a58e3351 23-Sep-2021 Li Qianruo <[email protected]>

Integer SRT16 Divider (#1019)

* New SRT4 divider that may improve timing

See "Digital reurrence dividers with reduced logical depth"

* SRT16 Int Divider that is working properly

* Fix bug r

Integer SRT16 Divider (#1019)

* New SRT4 divider that may improve timing

See "Digital reurrence dividers with reduced logical depth"

* SRT16 Int Divider that is working properly

* Fix bug related to div 1

* Timing improved version of SRT16 int divider

* Add copyright and made some minor changes

* Fix bugs related to div 0

* Fix another div 0 bug

* Fix another special case bug

show more ...


# f320e0f0 24-Jul-2021 Yinan Xu <[email protected]>

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.


# 0fb3674e 12-Jul-2021 Jiawei Lin <[email protected]>

Optimize timing of SRT4Divider (#875)


# c6d43980 04-Jun-2021 Lemover <[email protected]>

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.


# 2bd5334d 09-May-2021 Yinan Xu <[email protected]>

bundle: use Vec for src in ExuInput (#805)

This commit replaces src1, src2, src3 in Bundle ExuInput with Vec(3, UInt).
Should be easier for RS.


# 2225d46e 19-Apr-2021 Jiawei Lin <[email protected]>

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

show more ...


# c12bd822 09-Mar-2021 ljw <[email protected]>

Divider: opt state encoding (#672)


# afefbad5 23-Feb-2021 LinJiawei <[email protected]>

SRT4Divider: wrap data part in a data module


# f93cfde5 02-Feb-2021 LinJiawei <[email protected]>

SRT4Divider: opt timing


# 7c8efd4a 25-Jan-2021 Yinan Xu <[email protected]>

fu: fix needFlush arguments


# 9b09132d 25-Jan-2021 Yinan Xu <[email protected]>

Merge remote-tracking branch 'origin/master' into opt-exception


# 2d7c7105 25-Jan-2021 Yinan Xu <[email protected]>

redirect: split conditional redirect and unconditional redirect


# 4680597e 23-Jan-2021 Yinan Xu <[email protected]>

div: don't accept new request when it's cancelled


# d0d8f03a 21-Jan-2021 Yinan Xu <[email protected]>

exu,div: set io.in.valid though the instruction is flushed


# 7f1506e3 20-Dec-2020 LinJiawei <[email protected]>

[WIP] use berkeley-hardfloat in float units


# ff8496b2 10-Nov-2020 LinJiawei <[email protected]>

Divider: invalidate output when flush]


# 5018a303 08-Nov-2020 LinJiawei <[email protected]>

Divider: add a SRT-4 divider