feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI p

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI protoco
- Can don't using these modules by setting the option `HasMEMencryption`
& `HasBitmapCheck` to false

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feat(CSR): allow most CSRR can be out-of-order issued and executed

* Add some comment on rdata in NewCSR.
* Allow CSRR not to block backward instruction.
* Here is **Inorder** CSRR list,
* fflags,

feat(CSR): allow most CSRR can be out-of-order issued and executed

* Add some comment on rdata in NewCSR.
* Allow CSRR not to block backward instruction.
* Here is **Inorder** CSRR list,
* fflags, fcsr,
* vxsat, vcsr, vstart,
* mstatus, sstatus, hstatus, vsstatus, mnstatus,
* dcsr.
* The reason for Inorder CSRR executed is that these CSR will be changed
by Use-Level instruction without any fence, and executing OoO would
get wrong result.
* Since there must be FENCE before reading any PMC CSRs, there is no
need to let reading PMC CSRs inorder.

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feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check

feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check & ECC inject features
- Implement ICache ECC injection
- M-state software can write `eccctrl` to trigger error injection to meta/dataArray, next read can trigger auto-recovery (implemented in #3899)
- Remove custom CSR `Sfetchctl`

# Details
## CSR
The base address of the added mmio-mapped CSR is `0x38022080` and the registers is defined as below:
```
64 10 7 4 2 1 0
0x00 eccctrl | WARL | ierror | istatus | itarget | inject | enable |

64 PAddrBits-1 0
0x08 ecciaddr | WARL | paddr |
```
| CSR | field | desp |
| --- | --- | --- |
| eccctrl | enable | ECC check enable |
| eccctrl | inject | ECC inject enable (write 1 to trigger injection, read always 0) |
| eccctrl | itarget | ECC inject target<br>0: metaArray<br>1: rsvd<br>2: dataArray<br>3: rsvd |
| eccctrl | istatus | ECC inject status (read-only)<br>0: idle: inject controller idle, goes to working when received a inject request (i.e. write 1 to eccctrl.inject)<br>1: working: inject controller working, goes to injected when finished / error when failed<br>2: injected, goes to idle after read<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: error: inject failed (check eccctl.ierror for reason), goes to idle after read |
| eccctrl | ierror | ECC error reason (read-only, valid only if `eccctrl.istatus==error`)<br>0: ECC check is not enabled (i.e. `!eccctrl.enable`)<br>1: inject target invalid (i.e. `eccctrl.itarget==rsvd`)<br>2: inject addr (i.e. `ecciaddr.paddr`) not in ICache<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: rsvd |
| ecciaddr | paddr | Physical address of the inject target |

## Inject method
```asm
$INJECT_ADDR:
# maybe do something else
ret

test:
la t0, $BASE_ADDR # load icache control base addr
la t1, $INJECT_ADDR # load inject addr
jalr ra, 0(t1) # jump to injected addr to load it i
sd t1, 8(t0) # set inject addr
la t2, (target << 2 | 1 << 1 | 1 << 0) # load inject target & inject enable & ecc enable
sd t1, 0(t0) # set inject enable & ecc enable
loop:
ld t1, 0(t0) # get ecc control state
andi t1, t1, (0b11 << (4+1)) # get high bits of inject state
beqz t1, loop # if is idle, or working, loop

addi t1, t1, -1 # t1 = inject_state[2:1] - 1
bnez t1, error # if is not injected, error or rsvd

jalr ra, 0(t1) # jump to injected addr to trigger error
j finish

error:
# handle error
finish:
# finish
```
Or, checkout https://github.com/OpenXiangShan/nexus-am/pull/48

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accelerate read only csrr by pipelining

feat(riscv64): support RISC-V Smrnmi extension (#3480)

NewCSR: Refactor CSR about Debug

* add CSR: trigger csr & debug csr

* add CSR event: TrapEntryDEvent & DretEvent

* fixed trigger's comparison func between Consecutive pc and tdada2

NewCSR: modulized implementation

NewCSR: add Hypervisor CSRs

NewCSR: optimize dump fields using chisel3.reflect.DataMirror

NewCSR: add VirtualSupervisor CSRs

NewCSR: refactor VirtualSupervisor an

NewCSR: modulized implementation

NewCSR: add Hypervisor CSRs

NewCSR: optimize dump fields using chisel3.reflect.DataMirror

NewCSR: add VirtualSupervisor CSRs

NewCSR: refactor VirtualSupervisor and Hypervisor CSRs

* Make sure ValidIO etc function return CSREnumType not EnumType
* TODO: AIA for vs

NewCSR: add MachineLevel CSRs

NewCSR: fix alias relationship between hip, hvip and vsip

NewCSR: add SupervisorLevel CSRs

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CSR: remove useless sdsid custom-CSR (#2980)

Custom-CSR sdsid is a legacy from labeled XiangShan, which is no longer
in use. Remove this Custom-CSR.

This patch fixes OpenXiangShan/NEMU#329

Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

CSR: modify the write logic of satp, vsatp and hgatp; PageCache: fix some bugs about sfence

RVH: fix some syntax problems

RVH: finish the desigh of H extention

Merge remote-tracking branch 'upstream/master' into tmp-master

CSR: Correct the behavior of `ebreak` when hart not in debug mode

* `ebreak` instruction will raise breakpoint exception when hart not in debug mode.
* Use the signals renamed with "has*" to specify

CSR: Correct the behavior of `ebreak` when hart not in debug mode

* `ebreak` instruction will raise breakpoint exception when hart not in debug mode.
* Use the signals renamed with "has*" to specify the traps(exceptions/interrupts) are to be handled which were transported from ROB, while the signals renamed with "raise*" are being transported to ROB.

This commit is cherry-pick from nanhu and new-backend.

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CSR: add menvcfg and senvcfg CSR without function

The CSRs menvcfg and senvcfg are required by ISA and openSBI. To run openSBI, we merely include them without any functionality. The functionality ar

CSR: add menvcfg and senvcfg CSR without function

The CSRs menvcfg and senvcfg are required by ISA and openSBI. To run openSBI, we merely include them without any functionality. The functionality around these should be added in the feature.

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Merge remote-tracking branch 'upstream/master' into backendq

Debug Module: cherry-pick debug module from nanhu

csr: fix interrupt priority (#2480)

ICache: fix ICache ECC function (#2401)

Merge remote-tracking branch 'origin/master' into rf-after-issue

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

CSR: support vcsr

ICache: add parity check enable and prefetch enable control registers (#1406)

* Add Prefetch and Parity enable register for ICache

* Add ICache parity enable control for pipe

csr: add write mask to satp.ppn & xstatus.xs (#1323)

* csr.satp: add r/w mask of ppn part

* ci: add unit test, satp should concern PADDRBITS

* csr.xstatus: XS field is ready-only

* bump rea

csr: add write mask to satp.ppn & xstatus.xs (#1323)

* csr.satp: add r/w mask of ppn part

* ci: add unit test, satp should concern PADDRBITS

* csr.xstatus: XS field is ready-only

* bump ready-to-run

* bump ready-to-run, update nemu so

* fix typo

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Updated to priv 1.12 (#1301)

* csr: clear mstatus.mprv when mstatus.mpp != ModeM at xret

* csr: add mconfigptr, but hardwire to 0 now

* csr: add *BE to mstatusStruct which are hardwired to 0

Updated to priv 1.12 (#1301)

* csr: clear mstatus.mprv when mstatus.mpp != ModeM at xret

* csr: add mconfigptr, but hardwire to 0 now

* csr: add *BE to mstatusStruct which are hardwired to 0

* csr: fix bug of xret clear mprv

* ci: add unit test, xret clear mstatus.mprv when xpp is not M

* bump ready-to-run

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