fix merge error

backend: comments vector units temporarily

refactor(VPUSubModule): refactor VPUSubModule about src1NeedSew/immExt/src1Ext

func(UopDivType): support VEC_RGATHER/VEC_RGATHER_VX/VEC_RGATHEREI16 of UopDivType

refactor(VFPU): modify from 'VFPU extends FPUSubModule' to 'VFPU extends VPUSubModule'

pom(yunsuan): add IALU V3 (#2004)

1. func(VPERM): fix tail process, optimize vcompress, change vslide module name
2. func(VPERM): change to 2-stage
3. test(VPERM): add golden model and test: vslid

pom(yunsuan): add IALU V3 (#2004)

1. func(VPERM): fix tail process, optimize vcompress, change vslide module name
2. func(VPERM): change to 2-stage
3. test(VPERM): add golden model and test: vslidedown
4. test(VPERM): set vxsat=0 for vperm
5. test(VFADD): support vector-scalar operations func(VFADD): support vector-scalar operations
6. test: include
7. func(VFMA): add input:op_code,frs1,is_frs1; support vfmul.vv
8. func(VFMA):add vfmul.vf vfnmacc.vv vfnmacc.vf and their test supports
9. func(IALU):add IALU V3

* fix(decode): fix decode bug of selImm

1. fix decode bug of selImm
2. change VipuType to VpermType

* func(yunsuan): add VIAlu code v3

1. add VIAlu code v3
2. Update the IO of VFPU

* pom(yunsuan): add IALU V3

1. func(VPERM): fix tail process, optimize vcompress, change vslide module name
2. func(VPERM): change to 2-stage
3. test(VPERM): add golden model and test: vslidedown
4. test(VPERM): set vxsat=0 for vperm
5. test(VFADD): support vector-scalar operations func(VFADD): support vector-scalar operations
6. test: include <algorithm>
7. func(VFMA): add input:op_code,frs1,is_frs1; support vfmul.vv
8. func(VFMA):add vfmul.vf vfnmacc.vv vfnmacc.vf and their test supports
9. func(IALU):add IALU V3

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refactor(VIPU): optimize decoding logic of VIPU

1. Some logic moves from VIPU.scala to VPUSubModule.scala
2. add VIAluFix

func(vstart): add vstart from CSR to VIPU

func(vialu): add vialu & pass vadd (#1953)