style(Bundles): rewrite bundles with new style (#4274)

style(Bundles): move bundles to Bundles.scala (#4247)

area(backend): only pipe wakeupFromIQ and wakeupFromWB once

area(IssueQueue): encode exuOH as UInt to reduce storage (#4033)

fix(Backend): add vecLoadFinalIssueResp

fix(vlwakeup): fix vl write back wakeup from intExu or vfExu (#3643)

power(backend): add clock gate for Rob and IssueQueue (#3602)

timing(Backend): add OG2 stage for vector mem (#3482)

IssueQueue: only trans valid but not issued entry for fix ldCancel timing

IssueQueue: remove RegEnable for fix timing (#3275)

Backend: optimize og0 cancel signals (#3235)

* use Vec[Bool] instead of UInt for og0Cancel
* only wakeup source Exus containing 0-latency function unit should send
og0Cancel

chore: bump chisel 6.5.0 (#3210)

Backend & MemBlock: feedback use lqidx instead of robidx for fix timing and fix bug of vld feedback (#3189)

Backend&MemBlock: feedback use sqidx instead of robidx and uopidx for fix timing (#3172)

IssueQueue: change othersTransPolicy when allComp or allSimp for fix timing (#3120)

Backend: remove loadCancel from dispatch2iq to enqEntry for fix timing (#3105)

Entries: optimize timing of mem IQs' response signals (#3088)

BypassNetwork: ExuOH->ExuVec, add mask for forwardOrBypassValidVec3 (#3083)

Merge branch 'master' into vlsu-tmp-master

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the ol

rv64v: add ignore oldvd judgement in issue queue
1. when the instruction depend on old vd, we cannot set the srctype to imm
2. when vl = 0, we cannot set the srctype to imm because the vd keep the old value
3. when vl = vlmax, we can set srctype to imm when vta is not se

show more ...

Backend: add vector load border response

* The border response will be set success when the vector load uop pass to MemBlock like load

Backend: add vector load border response

* The border response will be set success when the vector load uop pass to MemBlock like load

Backend: support feedback for vector load/store

Backend: reduce the width of LoadDependency to 2 bits

IssueQueue, BypassNetwork: add 1 cycle delay when writing back to vf regfile