| #
fe73ba60 |
| 30-Apr-2024 |
Yangyu Chen <[email protected]> |
backend: prevent XSTile from being duplicated when generating multicore
Direct use of Map and Set in Scala will generate some lists in arbitrary
order in Chisel, causing duplicated XSTile when confi
backend: prevent XSTile from being duplicated when generating multicore
Direct use of Map and Set in Scala will generate some lists in arbitrary
order in Chisel, causing duplicated XSTile when configuring multicore.
This commit fixed it by converting some maps to lists and sorting the
segments using some key to prevent duplication from happening.
Signed-off-by: Yangyu Chen <[email protected]>
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| #
7e30d16c |
| 31-Jan-2024 |
Zhaoyang You <[email protected]> |
Zvbb: support Zvbb instruction (#2686)
* support vandn,vbrev,vbrev8,vrev8,vclz,vctz,vcpop,vrol,vror,vwsll
* bump yunsuan: support Zvbb
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| #
520f7dac |
| 22-Nov-2023 |
sinsanction <[email protected]> |
Backend: reduce imm width and move imm generating of instr fusion to enq
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| #
83ba63b3 |
| 11-Oct-2023 |
Xuan Hu <[email protected]> |
fix merge error
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| #
fe528fd6 |
| 25-Aug-2023 |
sinsanction <[email protected]> |
Backend, Fusion: support instruction fusion case 'lui + addi'
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| #
da778e6f |
| 19-May-2023 |
Xuan Hu <[email protected]> |
backend: add vector imm data path
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| #
d91483a6 |
| 28-Apr-2023 |
fdy <[email protected]> |
add vset support
Co-authored-by: zhanglyGit <[email protected]>
Co-authored-by: Xuan Hu <[email protected]>
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| #
730cfbc0 |
| 16-Apr-2023 |
Xuan Hu <[email protected]> |
backend: merge v2backend into backend
|