style(Bundles): rewrite bundles with new style (#4274)

style(Bundles): move bundles to Bundles.scala (#4247)

fix(scheduler): fix bug of sta valid

timing(zacas): move isDropAmocasSta logic gen from Scheduler to NewDispatch

area(backend): only pipe wakeupFromIQ and wakeupFromWB once

feat(backend): NewDispatch

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std uop for one cycle. This works fine on most of
the AMOs and LR/SC because they require only one std uop. However AMOCAS
requires at least two std uops, which may be issued from two separate
issue queues at the same time, leading to the loss of std uops.

This commit fixes this by taking all the outputs of the StdExeUnits into
account with arbitration logics.

fix(AtomicsUnit): DCache req can only be sent at `s_cache_req`

fix(AtomicsUnit, difftest): fix difftest io for atomic events

fix(MainPipe): fix precedence of `&` and `=/=` operator

fix(MainPipe): AMOCAS should not wait for AMOALU

fix(MemBlock): remove unnecessary assertion

fix(MainPipe): only CAS instruction can assert `s3_cas_fail`

fix(AtomicsUnit): fix bug in data select logic

submodule(difftest): bump difftest

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feat(Backend): add support for Zacas extension

misc: remove assert temporarily

busytable: support eliminate old vd when read vl's state

fix(Backend): add vecLoadFinalIssueResp

fix(vlwakeup): fix vl write back wakeup from intExu or vfExu (#3643)

refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in

refactor(HPM): move HPMs from utils to utility repo (#3631)

Because HPMs will be used in Coupled L2 as well, delete
`PerfCounterUtils.scala` in Xiangshan and create
`HardwarePerfMonitor.scala` in Utility.
See also [Pull Request in
CoupledL2](https://github.com/OpenXiangShan/CoupledL2/pull/251#discussion_r1770738535).

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timing(Backend): add OG2 stage for vector mem (#3482)

Backend: remove useless loadCancel for fix timing (#3374)

Scheduler, RegCache: add RegCacheTagTable to read reg cache state before entering issue queue

Backend: add reg cache data writing back path

Backend: optimize og0 cancel signals (#3235)

* use Vec[Bool] instead of UInt for og0Cancel
* only wakeup source Exus containing 0-latency function unit should send
og0Cancel

DataPath, BusyTable: remove unnecessary cancel signals (#3218)

* only non-load wakeup sources exu should send og0cancel
* og0cancel only works on the wakeup of 0 latency instructions

PerfEvent: refactor perfevents in Backend

* add `dispatch2Iq_out_fire_cnt`, `issueQueue_enq_fire_cnt`, `issueQueue_full` event in scheduler
* add busytable event
* move collecting perfevents from

PerfEvent: refactor perfevents in Backend

* add `dispatch2Iq_out_fire_cnt`, `issueQueue_enq_fire_cnt`, `issueQueue_full` event in scheduler
* add busytable event
* move collecting perfevents from `ctrlBlock` to `backend`
* change `perfEventsCtrl` into `perfEventsBackend`

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ResetPregStateReq: add isV0 isVl

Backend: change MaskSrcData VConfigData to V0Data VlData

Scheduler: support v0 & vl split

Backend: add Dispatch2IqFpImp

Merge branch 'master' into vlsu-merge-master-0504

Backend: add FpScheduler