History log of /XiangShan/src/main/scala/xiangshan/backend/regcache/RegCacheAgeTimer.scala (Results 1 – 3 of 3)
Revision Date Author Comments
# f25e75d9 22-Jul-2024 sinsanction <[email protected]>

RegCacheAgeTimer: add random values to the low bits of age timers, avoid replacing the same item in multiple consecutive cycles when reg cache is full


# f8124f70 05-Jul-2024 sinsanction <[email protected]>

RegCacheAgeTimer: optimize the initial state of the AgeTimer


# 86102875 28-Jun-2024 sinsanction <[email protected]>

RegCache: add Main Module, Data Module, Age Timer, Age Detector of RegCache