| #
748214a1 |
| 20-Dec-2024 |
xiaofeibao <[email protected]> |
area(dataPath): set fpRegfile and vecRegfile's splictNum to 4
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| #
771a6ec2 |
| 09-Dec-2024 |
xiaofeibao <[email protected]> |
timing(intRegfile): use IntRegFileSplit for better timing
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| #
8537b88a |
| 20-Aug-2024 |
Tang Haojin <[email protected]> |
Top: add XSTileWrap for async signals (#3400)
Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: zhaohong1988 <[email protected]>
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| #
60052a3f |
| 27-Jul-2024 |
xiaofeibao <[email protected]> |
Regfile: vl reset to 0, add instance name and module name for regfile
|
| #
fbe46a0a |
| 29-May-2024 |
xiaofeibao <[email protected]> |
DataConfig: remove VfRegSrcDataSet
|
| #
07b5cc60 |
| 29-May-2024 |
xiaofeibao <[email protected]> |
Backend: change MaskSrcData VConfigData to V0Data VlData
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| #
2aa3a761 |
| 27-May-2024 |
sinsanction <[email protected]> |
Backend: add some basic signals for v0 & vl split
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| #
60f0c5ae |
| 26-Apr-2024 |
xiaofeibao <[email protected]> |
Backend: add FpScheduler
|
| #
19203128 |
| 06-Feb-2024 |
xiaofeibao-xjtu <[email protected]> |
Regfile: add require for bankNum
|
| #
b8ca25cb |
| 31-Jan-2024 |
xiaofeibao-xjtu <[email protected]> |
Int Regfile: Split-bank read
|
| #
6e8ad5a5 |
| 04-Jan-2024 |
xiaofeibao-xjtu <[email protected]> |
RegFile: og0's raddr piped
|
| #
1e6c281a |
| 18-Dec-2023 |
xiaofeibao-xjtu <[email protected]> |
Regfile: avoid priority write
|
| #
4b0d80d8 |
| 11-Oct-2023 |
Xuan Hu <[email protected]> |
Merge upstream/master into tmp-backend-merge-master
|
| #
60c0bc56 |
| 06-Oct-2023 |
Haojin Tang <[email protected]> |
RegFile: remove data field in `RfReadPortWithConfig`
|
| #
8891a219 |
| 08-Oct-2023 |
Yinan Xu <[email protected]> |
Bump rocket-chip (#2353)
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| #
39c59369 |
| 03-Aug-2023 |
Xuan Hu <[email protected]> |
params,backend: refactor RegFile parameters
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| #
c0be7f33 |
| 19-Jul-2023 |
Xuan Hu <[email protected]> |
backend,iq: split wake up bundles, add cancel bundle
* Split IssueQueueWakeUpBundle into IssueQueueWBWakeUpBundle and IssueQueueIQWakeUpBundle.
* Add cancel bundle used to cancel waked-up uop src
*
backend,iq: split wake up bundles, add cancel bundle
* Split IssueQueueWakeUpBundle into IssueQueueWBWakeUpBundle and IssueQueueIQWakeUpBundle.
* Add cancel bundle used to cancel waked-up uop src
* Add srcTimer in StatusArray to record the cycles src has been waked up
* Add dataSources in StatusArray to record the source of src data (reg, forward, bypass or none)
* Remove useless ready field in StatusArray
show more ...
|
| #
b6b11f60 |
| 22-May-2023 |
Xuan Hu <[email protected]> |
backend: add vector related datapath and configs
|
| #
a8db15d8 |
| 10-May-2023 |
fdy <[email protected]> |
backend: refactor vset and add rab support
|
| #
730cfbc0 |
| 16-Apr-2023 |
Xuan Hu <[email protected]> |
backend: merge v2backend into backend
|
| #
3dca89ec |
| 14-Mar-2023 |
Xuan Hu <[email protected]> |
regfile: changed to sync regfile
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| #
027c9765 |
| 07-Feb-2023 |
Xuan Hu <[email protected]> |
backend: update Regfile
set the number of entries in constructor of Regfile class not in XSParameters
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| #
16a511c2 |
| 06-Feb-2023 |
Xuan Hu <[email protected]> |
backend: split non-return regfile in another file
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| #
aa825ab5 |
| 02-Feb-2023 |
Xuan Hu <[email protected]> |
v2backend: add non-return regfile object
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| #
9ab1568e |
| 15-Nov-2022 |
czw <[email protected]> |
rs: mv rf-read from dispatch2rs to rs-select(asyn read regfile now)
chore(*): Change Sequential Parameter Pass to Parameter Name Parameter Passing
refactor(Regfile): Modify Synchronous Read to Asyn
rs: mv rf-read from dispatch2rs to rs-select(asyn read regfile now)
chore(*): Change Sequential Parameter Pass to Parameter Name Parameter Passing
refactor(Regfile): Modify Synchronous Read to Asynchronous Read
refactor(Scheduler, ReservationStationBase): Connect the asynchronous read port of the register and the reserved station
1. add parameter( numIntRfReadPorts, numFpRfReadPorts, params.exuCfg)
2. fix extractReadRf
3. remove dataArray and add dataArrayWrite, dataArrayMultiWrite,
s1_out_addr
4. add immBypassedData2 for bypass and fix DataSelect
refactor(ReservationStationStd): fix connect between s1_deqRfDataSel and readFpRf_asyn(i).data
refactor(ReservationStationJump): add jalrMem and fix immExts connect
show more ...
|