History log of /XiangShan/src/main/scala/xiangshan/backend/rename/CompressUnit.scala (Results 1 – 5 of 5)
Revision Date Author Comments
# b720b0cd 30-Oct-2024 chengguanghui <[email protected]>

fix(trace): fix `tracePipe` in pipeline

* fix itype for branch after writeback
* update itype to DeqGroup when branch instruction commit at next cycle after writeback.
* fix ftqoffset in commitIn

fix(trace): fix `tracePipe` in pipeline

* fix itype for branch after writeback
* update itype to DeqGroup when branch instruction commit at next cycle after writeback.
* fix ftqoffset in commitInfo for fuse instruction
* fix `iretire` in rename

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# c49ebec8 18-Nov-2024 Haoyuan Feng <[email protected]>

docs: add acknowledgements (#3861)


# 7e0f64b0 21-Aug-2024 Guanghui Cheng <[email protected]>

Trigger: refactor trigger information in pipeline. (#3403)


# 83ba63b3 11-Oct-2023 Xuan Hu <[email protected]>

fix merge error


# 89cc69c1 11-Aug-2023 Tang Haojin <[email protected]>

Rob: support ROB compression (#2192)

For consecutive instructions that do not raise exceptions,
they can share a same rob entry and reduce rob consumption.

Only scalar instructions are supported no

Rob: support ROB compression (#2192)

For consecutive instructions that do not raise exceptions,
they can share a same rob entry and reduce rob consumption.

Only scalar instructions are supported now.

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Co-authored-by: fdy <[email protected]>

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