fix(rename): fix Csrr format (#4605)

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

show more ...

fix(csr): CSRR instruction read xireg inOrder (#4393)

* AIA registers are designed to be access asynchronously, so newCSR will
wait for response. Therefore, CSRR instruction read mireg/sireg/vsireg

fix(csr): CSRR instruction read xireg inOrder (#4393)

* AIA registers are designed to be access asynchronously, so newCSR will
wait for response. Therefore, CSRR instruction read mireg/sireg/vsireg
inOrder.

show more ...

feat(CSR): allow most CSRR can be out-of-order issued and executed

* Add some comment on rdata in NewCSR.
* Allow CSRR not to block backward instruction.
* Here is **Inorder** CSRR list,
* fflags,

feat(CSR): allow most CSRR can be out-of-order issued and executed

* Add some comment on rdata in NewCSR.
* Allow CSRR not to block backward instruction.
* Here is **Inorder** CSRR list,
* fflags, fcsr,
* vxsat, vcsr, vstart,
* mstatus, sstatus, hstatus, vsstatus, mnstatus,
* dcsr.
* The reason for Inorder CSRR executed is that these CSR will be changed
by Use-Level instruction without any fence, and executing OoO would
get wrong result.
* Since there must be FENCE before reading any PMC CSRs, there is no
need to let reading PMC CSRs inorder.

show more ...

fix(Rename): fuse lui-load only if `rfWen` of lui is true (#4131)

timing(zacas): move isDropAmocasSta logic gen from Scheduler to NewDispatch

feat(backend): NewDispatch

fix(trace): remove traceTrap & tracePriv from trace pipeline

fix(trace): fix `tracePipe` in pipeline

* fix itype for branch after writeback
* update itype to DeqGroup when branch instruction commit at next cycle after writeback.
* fix ftqoffset in commitIn

fix(trace): fix `tracePipe` in pipeline

* fix itype for branch after writeback
* update itype to DeqGroup when branch instruction commit at next cycle after writeback.
* fix ftqoffset in commitInfo for fuse instruction
* fix `iretire` in rename

show more ...

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std uop for one cycle. This works fine on most of
the AMOs and LR/SC because they require only one std uop. However AMOCAS
requires at least two std uops, which may be issued from two separate
issue queues at the same time, leading to the loss of std uops.

This commit fixes this by taking all the outputs of the StdExeUnits into
account with arbitration logics.

fix(AtomicsUnit): DCache req can only be sent at `s_cache_req`

fix(AtomicsUnit, difftest): fix difftest io for atomic events

fix(MainPipe): fix precedence of `&` and `=/=` operator

fix(MainPipe): AMOCAS should not wait for AMOALU

fix(MemBlock): remove unnecessary assertion

fix(MainPipe): only CAS instruction can assert `s3_cas_fail`

fix(AtomicsUnit): fix bug in data select logic

submodule(difftest): bump difftest

show more ...

feat(Backend): add support for Zacas extension

misc: remove assert temporarily

fix(vector): do not set vs.dirty for some type of vecInsts (#3965)

fix(HPM): fix PTW perfevent print error, organize the code format of some perfevents (#3890)

`getperfevent` retrieves both the `name` and `value` fields, whereas
`getperf` only retrieves the `value

fix(HPM): fix PTW perfevent print error, organize the code format of some perfevents (#3890)

`getperfevent` retrieves both the `name` and `value` fields, whereas
`getperf` only retrieves the `value` port. The original implementation
caused all perf event information for PTW to be printed as
`perfEventsPTW`, making them indistinguishable.

show more ...

fix(Rename): remove the handling of dest being src in bypassCond (#3752)

feat(rv64v): support first only fault instruction

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs f

build: enable always-basic-diff for make verilog (#3574)

This commit turns on basic difftest features again, no matter it's for
simulation or physical design. This commit aims at allowing designs for
physical design to be verified.

show more ...

timing(Backend): remove useless ldest=/=0.U logic because rfWen will be false

Backend: stop block_backward for csrr, in rename stage

accelerate read only csrr by pipelining

Rob: fix bug of rob commit. (#3418)

In this PR, the main goal is to fix the bug encountered during ROB
commit. However, resolving this issue requires information about
`iretire` and `ilastsize`, w

Rob: fix bug of rob commit. (#3418)

In this PR, the main goal is to fix the bug encountered during ROB
commit. However, resolving this issue requires information about
`iretire` and `ilastsize`, which need be collected by the trace.
Therefore, I have also included the trace interface in this PR.

The specific changes are as follows:
* When rob commit, update the ftqIdx and ftqOffset to correctly notify
the frontend which instructions have been committed.
* In each robentry, the ftqIdx and ftqOffset belong to the first
instruction that was compressed, that is Necessary when exceptions
happen.
* Add trace Interface in hart.
* Add trace parameter in parameter.scala.
* Collect trace infomation in backend pipeline.

show more ...

Trigger: refactor trigger information in pipeline. (#3403)

DebugModule: Fix bug of singleStep. (#3395)

* `SingleStepStatus` should not be cleared by redirect before hart enter
debugMode.
* singleStep should block rob compress in `rename`.

Backend: change ready logic from dispatch to decode for better performance

Scheduler, RegCache: add RegCacheTagTable to read reg cache state before entering issue queue

Rob: fix bug of exception (#3161)

1.when writeback exception, rob may commit next cycle. 2.when fulshOut,
rob commit info to ftq may 4 cycle after redirect but redirect info to
ftq need 5 cycle.