timing(backend): pipe robCommits for better timing and area

Rename: fix debug_v0_rat debug_vl_rat connection

backend: new rob 8 banks read and 8 commit width

Backend: add clock gating to valid singal

Rab: shrink rab entry width

snapshot: flush conditionally when redirect comes

Merge upstream/master into tmp-backend-merge-master

backend: parameterized generation debug IO and difftest IO

Bump rocket-chip (#2353)

fix errors in merge master into new-backend

CtrlBlock: implement rename snapshot (#2191)

* CtrlBlock: new ME method for better timing and area

* ctrlblock: implement snapshot recovery

* rename: enlarge distance between snapshots

* sn

CtrlBlock: implement rename snapshot (#2191)

* CtrlBlock: new ME method for better timing and area

* ctrlblock: implement snapshot recovery

* rename: enlarge distance between snapshots

* snapshot: add rename snapshot switch

* CtrlBlock: add snapshotGen API

* snapshot: optimize timing

* snapshot: put snapshot logic in a module

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CtrlBlock: new ME method for better timing and area (#2161)

new move elimination method:

1. get old_pdest from arch-rat when commit;
2. get ready-for-free from comparing old-pdest with arch-rat

CtrlBlock: new ME method for better timing and area (#2161)

new move elimination method:

1. get old_pdest from arch-rat when commit;
2. get ready-for-free from comparing old-pdest with arch-rat after commit;

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Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

rename: Re-rename instead of walking back after redirect (#1768)

* freelist & refcounter: implement arch states

* walk: restore and walk again when redirecting

* ROB: optimize invalidation of

rename: Re-rename instead of walking back after redirect (#1768)

* freelist & refcounter: implement arch states

* walk: restore and walk again when redirecting

* ROB: optimize invalidation of `valid`

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dpq: optimize read and write timing of data module (#1610)

This commit changes the data modules in Dispatch Queue. We use one-hot
indices to read and write the data array.

freelist: optimize timing of read and writing (#1593)

This commit optimizes the timing of freelist by changing the updating
function of headPtr and tailPtr.

We maintains an one-hot representatio

freelist: optimize timing of read and writing (#1593)

This commit optimizes the timing of freelist by changing the updating
function of headPtr and tailPtr.

We maintains an one-hot representation of headPtr and further uses it to
read the free registers from the list, which should be better than the
previous implementation where headPtr is used to indexed into the queue.

The update of tailPtr and the freelist is delayed by one cycle to
optimize the timing. Because freelist allocates new registers in the
next cycle iff there are more than RenameWidth free registers in this
cycle. The freed registers in this cycle will never be used in the next
cycle. Thus, we can delay the updating of queue data to the next cycle.
We also move the update of tailPtr to the next cycle, since PopCount
takes a long timing and we move the last adder to the next cycle. Now
the adder works parallely with PopCount. That is, the updating of
tailPtr is pipelined.

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rename: support full-featured move elimination (#1123)

This commit optimizes the move elimination implementation.

Reference counting for every physical register is recorded. Originally
0-31 regi

rename: support full-featured move elimination (#1123)

This commit optimizes the move elimination implementation.

Reference counting for every physical register is recorded. Originally
0-31 registers have counters of ones. Every time the physical register
is allocated or deallocated, the counter is increased or decreased by
one. When the counter becomes zero from a non-zero value, the register
is freed and released to freelist.

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