area(trace, pcMem): Trace only get `startAddr` from pcmem

fix(trace): add pipe for traceCoreInterface in memblock and l2top

fix(trace): remove traceTrap & tracePriv from trace pipeline

feat(trace): add TraceCoreInterface in top.

feat(trace): add trace buffer.

Rob: fix bug of rob commit. (#3418)

In this PR, the main goal is to fix the bug encountered during ROB
commit. However, resolving this issue requires information about
`iretire` and `ilastsize`, w

Rob: fix bug of rob commit. (#3418)

In this PR, the main goal is to fix the bug encountered during ROB
commit. However, resolving this issue requires information about
`iretire` and `ilastsize`, which need be collected by the trace.
Therefore, I have also included the trace interface in this PR.

The specific changes are as follows:
* When rob commit, update the ftqIdx and ftqOffset to correctly notify
the frontend which instructions have been committed.
* In each robentry, the ftqIdx and ftqOffset belong to the first
instruction that was compressed, that is Necessary when exceptions
happen.
* Add trace Interface in hart.
* Add trace parameter in parameter.scala.
* Collect trace infomation in backend pipeline.

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