chore: fix several deprecation warning (#4352)

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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build: purge chisel 3 and add deprecation check (#3250)

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies th

perf: use perfUtils in `Utility` (#3190)

Currently, log and perf utilities such as `XSPerfAccumulate` are
implemented in many repositories like XiangShan, CoupledL2 and HuanCun.
This PR unifies them and put them in Utility repository.

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memblock: add rest clockgate of reg (#3017)

Co-authored-by: cai luoshan <[email protected]>
Co-authored-by: Cai Luoshan <[email protected]>
Co-authored-by: good-circle <

memblock: add rest clockgate of reg (#3017)

Co-authored-by: cai luoshan <[email protected]>
Co-authored-by: Cai Luoshan <[email protected]>
Co-authored-by: good-circle <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: CharlieLiu <[email protected]>

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L1CacheErrorInfo: code refactor for correct and convenient clockgate (#3044)

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

mem: split L1CacheErrorInfo and L1BusErrorUnitInfo, fix ecc error (#1409)

* mem: fix error csr update

* dcache: l2 error will now trigger atom error

* chore: fix cache error debug decoder

* mem:

mem: split L1CacheErrorInfo and L1BusErrorUnitInfo, fix ecc error (#1409)

* mem: fix error csr update

* dcache: l2 error will now trigger atom error

* chore: fix cache error debug decoder

* mem: split L1CacheErrorInfo and L1BusErrorUnitInfo

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mem: refactor l1 error implementation (#1391)

* dcache: add source info in L1CacheErrorInfo

* ICache: fix valid signal and add source/opType

* dcache: fix bug in ecc error

* mem,csr: send f

mem: refactor l1 error implementation (#1391)

* dcache: add source info in L1CacheErrorInfo

* ICache: fix valid signal and add source/opType

* dcache: fix bug in ecc error

* mem,csr: send full L1CacheErrorInfo to CSR

* icache: provide cache error info for CSR

* dcache: force resp hit if tag ecc error happens

* mem: reorg l1 cache error report path

Now dcache tag error will force trigger a hit

* dcache: fix readline ecc check error

* dcache: mainpipe will not be influenced by tag error

* dcache: fix data ecc check error

* dcache: if coh state is Nothing, do not raise error

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: JinYue <[email protected]>

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Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction

Co-authored-by: Zhang

Refactor top (#1093)

* Temporarily disable TLMonitor

* Bump huancun (L2/L3 MSHR bug fix)

* Refactor Top

* Bump huancun

* alu: fix bug of rev8 & orc.b instruction

Co-authored-by: Zhangfw <[email protected]>

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128KB L1D + non-inclusive L2/L3 (#1051)

* L1D: provide independent meta array for load pipe

* misc: reorg files in cache dir

* chore: reorg l1d related files

* bump difftest: use clang to c

128KB L1D + non-inclusive L2/L3 (#1051)

* L1D: provide independent meta array for load pipe

* misc: reorg files in cache dir

* chore: reorg l1d related files

* bump difftest: use clang to compile verialted files

* dcache: add BankedDataArray

* dcache: fix data read way_en

* dcache: fix banked data wmask

* dcache: replay conflict correctly

When conflict is detected:
* Report replay
* Disable fast wakeup

* dcache: fix bank addr match logic

* dcache: add bank conflict perf counter

* dcache: fix miss perf counters

* chore: make lsq data print perttier

* dcache: enable banked ecc array

* dcache: set dcache size to 128KB

* dcache: read mainpipe data from banked data array

* dcache: add independent mainpipe data read port

* dcache: revert size change

* Size will be changed after main pipe refactor

* Merge remote-tracking branch 'origin/master' into l1-size

* dcache: reduce banked data load conflict

* MainPipe: ReleaseData for all replacement even if it's clean

* dcache: set dcache size to 128KB

BREAKING CHANGE: l2 needed to provide right vaddr index to probe l1,
and it has to help l1 to avoid addr alias problem

* chore: fix merge conflict

* Change L2 to non-inclusive / Add alias bits in L1D

* debug: hard coded dup data array for debuging

* dcache: fix ptag width

* dcache: fix amo main pipe req

* dcache: when probe, use vaddr for main pipe req

* dcache: include vaddr in atomic unit req

* dcache: fix get_tag() function

* dcache: fix writeback paddr

* huancun: bump version

* dcache: erase block offset bits in release addr

* dcache: do not require probe vaddr != 0

* dcache: opt banked data read timing

* bump huancun

* dcache: fix atom unit pipe req vaddr

* dcache: simplify main pipe writeback_vaddr

* bump huancun

* dcache: remove debug data array

* Turn on all usr bits in L1

* Bump huancun

* Bump huancun

* enable L2 prefetcher

* bump huancun

* set non-inclusive L2/L3 + 128KB L1 as default config

* Use data in TLBundleB to hint ProbeAck beeds data

* mmu.l2tlb: mem_resp now fills multi mq pte buffer

mq entries can just deq without accessing l2tlb cache

* dcache: handle dirty userbit

* bump huancun

* chore: l1 cache code clean up

* Remove l1plus cache
* Remove HasBankedDataArrayParameters

* Add bus pmu between L3 and Mem

* bump huncun

* dcache: fix l1 probe index generate logic

* Now right probe index will be used according to the len of alias bits

* dcache: clean up amo pipeline

* DCacheParameter rowBits will be removed in the future, now we set it to 128
to make dcache work

* dcache: fix amo word index

* bump huancun

Co-authored-by: William Wang <[email protected]>
Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: TangDan <[email protected]>
Co-authored-by: ZhangZifei <[email protected]>
Co-authored-by: wangkaifan <[email protected]>

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