style(LoadPipe): use `miss_req.bits.cancel` instead of `mq_enq_cancel` (#4296)

fix(DCache): pass `amo_cmp` to MSHR when cas req miss (#4272)

fix(LSU): fix cbo instruction exception handling logic (#4215)

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bo

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch
Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.

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fix(MemBlock): support non-data error handling for cacheable region (#4093)

When DCache refill reponses with `denied` or `corrupt` asserted, the
loads belonging to the cache line should report load

fix(MemBlock): support non-data error handling for cacheable region (#4093)

When DCache refill reponses with `denied` or `corrupt` asserted, the
loads belonging to the cache line should report load access fault. This
is accomplished by including a `corrupt` bit in the DCache MSHR
forwarding and TileLink channel D forwarding logic and triggering
excepion when `corrupt` is detected.

Store non-data error that comes from DCache store miss is unable to
trigger a precise access fault trap but an imprecise bus-error
interrupt. And it will be included in another commit.

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feat(XSPerf): count histogram of larger Ld-to-use latency (#4083)

- Latency of < 100 is not enough for performance analysis
- To reduce outputs, use larger bucket (30 per bucket)

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std uop for one cycle. This works fine on most of
the AMOs and LR/SC because they require only one std uop. However AMOCAS
requires at least two std uops, which may be issued from two separate
issue queues at the same time, leading to the loss of std uops.

This commit fixes this by taking all the outputs of the StdExeUnits into
account with arbitration logics.

fix(AtomicsUnit): DCache req can only be sent at `s_cache_req`

fix(AtomicsUnit, difftest): fix difftest io for atomic events

fix(MainPipe): fix precedence of `&` and `=/=` operator

fix(MainPipe): AMOCAS should not wait for AMOALU

fix(MemBlock): remove unnecessary assertion

fix(MainPipe): only CAS instruction can assert `s3_cas_fail`

fix(AtomicsUnit): fix bug in data select logic

submodule(difftest): bump difftest

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feat(DCache): merge CMO requests into DCache TL-A Channel (#3968)

* remove previous cmo datapath in memblock.
* add datapath for cmo requests between lsq and dcache.
* add new CMOUnit in MissQueue

feat(DCache): merge CMO requests into DCache TL-A Channel (#3968)

* remove previous cmo datapath in memblock.
* add datapath for cmo requests between lsq and dcache.
* add new CMOUnit in MissQueue.
* bump rocket-chip & coupledL2.

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docs: add acknowledgements (#3861)

timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Opt

timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Optimize VLSU feedback and redirect
+ Optimise ldCancel and writeback signal generation
+ Optimise TLB Query Vaddr/hlv/hlvx/valid etc
+ Delay MMIO Store writeback for 1 Cycle
+ Fix tlbNoQuery and pmp logic
+ Remove clock gating for s3_fast_rep
+ Remove wbq conflict check to LoadPipe/MainPipe
+ Remove Mux in dcache resp data
+ Optimise data generation logic of LoadUnit
+ Duplicate Register in LoadUnit for data writeback
+ Duplicate Register in loadPipe for missQueue enq
+ Add skid buffer in VLSU
+ Select data from metaArray at S1
+ Simplify the enqueuing logic of missQueue
+ Separately generate the ready logic of miss Queue
+ Relax the conditions valid for bankdataArray reads
+ Add Reg between Dcache Mainpipe with sms prefetcher
+ Optimise store exceptionBuffer pipeline

---------

Co-authored-by: weiding liu <[email protected]>
Co-authored-by: Charlie Liu <[email protected]>
Co-authored-by: good-circle <[email protected]>

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DCache: Block conflicting replacement for whole mshr lifecycle

DCache: Replay refill_req when the evict_addr matching a valid mshr

LSQ: optimize static clock gating coverage and fix x_value in vcs (#3176)

optimize LSQ static clock gating coverage, fix x_value in vcs

DCache: Fix valid signal of refill_info and error_flag_write

DCache: Block the writeback req when the addr matching a valid req in mshr (#3179)

Bug:
- When two req with different addr x and y enter MissQueue together, req
y is real miss req, while req x is

DCache: Block the writeback req when the addr matching a valid req in mshr (#3179)

Bug:
- When two req with different addr x and y enter MissQueue together, req
y is real miss req, while req x is **AcquireBlock BtoT**. Req y receive
the resp from L2 first and complete the refill operation by replacing
the data block with addr x (decided by plru algorithm). MainPipe will
release the data block with addr in writeback queue through req
**Release BtoN** to L2. Addr x receive GrantData with permission toT at
last.
- From the view of L2, the req sequence of addr x is: Acquire BtoT ->
GrantData toT -> Release BtoN, which is abnormal.

Fix: When a valid req reaches wbq, check if there is any valid mshr with
same block_addr. If a mshr is found, block current wbq_req.

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memblock: add rest clockgate of reg (#3017)

Co-authored-by: cai luoshan <[email protected]>
Co-authored-by: Cai Luoshan <[email protected]>
Co-authored-by: good-circle <

memblock: add rest clockgate of reg (#3017)

Co-authored-by: cai luoshan <[email protected]>
Co-authored-by: Cai Luoshan <[email protected]>
Co-authored-by: good-circle <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: CharlieLiu <[email protected]>

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DCache: Move L2 refill error signal to refill_info (#3063)

Error signal for L2 refill request is generated when mem_grant but sent
to MainPipe in mainpipe_req with l2_hint, which is not correct.
M

DCache: Move L2 refill error signal to refill_info (#3063)

Error signal for L2 refill request is generated when mem_grant but sent
to MainPipe in mainpipe_req with l2_hint, which is not correct.
Move error signal to refill_info now.

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MissQueue: fix bug: 'isKeyword' update when miss req merge (#2972)

MissQueue：fix bug: 'isKeyword' update when miss req merge

Bump utility and disable ConstantIn by default (#2955)

* use BigInt for initValue of Constantin.createRecord
* use WITH_CONSTANTIN=1 to enable the ConstantIn plugin

DCache: Fix X propagation problem (#2933)

DCache: New feature evict on refill (#2919)

- Remove module RefillPipe, move DCache replacer access/update to
MainPipe.
- Using l2_hint as an early wake-up signal for MSHR.

---------

Co-auth

DCache: New feature evict on refill (#2919)

- Remove module RefillPipe, move DCache replacer access/update to
MainPipe.
- Using l2_hint as an early wake-up signal for MSHR.

---------

Co-authored-by: YukunXue <[email protected]>
Co-authored-by: Tang Haojin <[email protected]>
Co-authored-by: ssszwic <[email protected]>
Co-authored-by: Kunlin You <[email protected]>

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MemBlock: consider valids for assertions (#2870)

Configs: correct MaxHartIdBits (#2838)

Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This

Configs: correct MaxHartIdBits (#2838)

Currently, many different lengths of HartId in Xiangshan, making it hard to
configure it to scale more than 16 cores since we have set 4bits somewhere.
This commit corrects MaxHartIdBits in config and uses MaxHartIDBits where
it needs to get this solved.

Signed-off-by: Yangyu Chen <[email protected]>

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chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`

Feature keyword priority (#2562)

* "isKeyword" priority & debug( modify load fwd mshr data):

*Bundle: add "isKeyword" in L2ToL1Hint

*XSCore/XSTile/MemBlock: modify l2_hint assignment,(

Feature keyword priority (#2562)

* "isKeyword" priority & debug( modify load fwd mshr data):

*Bundle: add "isKeyword" in L2ToL1Hint

*XSCore/XSTile/MemBlock: modify l2_hint assignment,(add isKeyword)

*DCacheWrapper: add lqidx for compare age, add IsKeywordField

*LoadPipe: add lqIdx for miss_req

*MissQueue: add "isKeyword" logic for miss entries, MissReqPipeReg
transfer "isKeyword" from L1 to L2 by mem_acquire
modify refill_to_ldq 's addr/data logic depending on
"isKeyword"
modify load forward data from mshr logic

*LoadQueueReplay: modify replay order by l2_hint

*LoadUnit: add lqIdx in dcache_req

* modify iskeyword 'user' to 'echo', load forward data from tlbundle D

* L2TOP: modify l2_hint type, add l2_hint_iskeyword

* LRQ: add l2_hint xsperf counter

* modify merge conflict:
loadunit: name changed so_uop --> so_select_src.uop

* DCacheWrapper: modify tl_channel_D 2 beats both can fwd data

* dump coupledL2 : Feature favor l1 d keyword priority (#87)

* Fix fma rm (#2586)

* bump fudian

* fma: fix bug of fadd's rm

* FMA: fix bug of fadd's rm

* dump : coupledL2 branch:feature-favor-L1D-keyword-priority

* dump coupledL2

---------

Co-authored-by: xiaofeibao-xjtu <[email protected]>

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