style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

bpu: duplicate most possible signal related to npc generation to address (#2254)

high fanout problems

Co-authored-by: Lingrui98 <[email protected]>

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

bpu: refactor prediction i/o bundles

bpu: refactor BranchPredictionUpdate bundle

Previously the BranchPredictionUpdate bundle was inherited from
BranchPredictionBundle, and that made some field of the bundle
unused. It was hard to find

bpu: refactor BranchPredictionUpdate bundle

Previously the BranchPredictionUpdate bundle was inherited from
BranchPredictionBundle, and that made some field of the bundle
unused. It was hard to find which signals are really in use.
Now we make BranchPredictionUpdate a independent bundle, so that
the signals in it are all in use.

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bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* le

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

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bpu: disable bim

ubtb: refactor prediction mechanism(temp commit)

bpu: remove stage 3

bpu: extract wrbypass to be a module

frontend: let br/jmp share the last slot of an ftb entry, ghist update timing optimization

frontend: code clean ups

frontend: remove deprecated code

Merge branch 'master' into merge-master

misc: update PCL information (#899)

XiangShan is jointly released by ICT and PCL.

[WIP]BPU: Decoupled frontend BPU design

Add MulanPSL-2.0 License (#824)

In this commit, we add License for XiangShan project.

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's

Refactor parameters, SimTop and difftest (#753)

* difftest: use DPI-C to refactor difftest

In this commit, difftest is refactored with DPI-C calls.
There're a few reasons:
(1) From Verilator's manual, DPI-C calls should be more efficient than accessing from dut_ptr.
(2) DPI-C is cross-platform (Verilator, VCS, ...)
(3) difftest APIs are splited from emu.cpp to possibly support more backend platforms
(NEMU, Spike, ...)

The performance at this commit is quite slower than the original emu.
Performance issues will be fixed later.

* [WIP] SimTop: try to use 'XSTop' as soc

* CircularQueuePtr: ues F-bounded polymorphis instead implict helper

* Refactor parameters & Clean up code

* difftest: support basic difftest

* Support diffetst in new sim top

* Difftest; convert recode fmt to ieee754 when comparing fp regs

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Debug: add int/exc inst wb to debug queue

* Difftest: pass sign-ext pc to dpic functions && fix exception pc

* Difftest: fix naive commit num limit

Co-authored-by: Yinan Xu <[email protected]>
Co-authored-by: William Wang <[email protected]>

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Refactor XSPerf, now we have three XSPerf Functions.
XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can est

Refactor XSPerf, now we have three XSPerf Functions.
XSPerfAccumulate: sum up performance values.
XSPerfHistogram: count the occurrence of performance values, split them
into bins, so that we can estimate their distribution.
XSPerfMax: get max of performance values.

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IFU: add performance counters (#649)

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for

IFU: add performance counters (#649)

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

* sc: restrict threshold update conditions and prevent overflow problem

* sc: use seperative thresholds for each bank

* sc: update debug info

* sc: use adaptive threshold algorithm from the original O-GEHL

* tage, bim, sc: optimize wrbypass logic

* sc: initialize threshold to 60

* loop: remove unuseful RegNext on redirect

* ifu: add perf counters

* Perf: Add loopPredictor perf counters

* sc: fix perf logics

Co-authored-by: jinyue110 <[email protected]>
Co-authored-by: zoujr <[email protected]>

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BPU: enable TAGE-SC (#646)

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

*

BPU: enable TAGE-SC (#646)

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

* sc: restrict threshold update conditions and prevent overflow problem

* sc: use seperative thresholds for each bank

* sc: update debug info

* sc: use adaptive threshold algorithm from the original O-GEHL

* tage, bim, sc: optimize wrbypass logic

* sc: initialize threshold to 60

* loop: remove unuseful RegNext on redirect

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Fix uncache (#635)

* Replacement: change state in way method.

* State change is also needed when miss occurs, otherwise we will choose
a way that has been just refilled into cache as the victim.

Fix uncache (#635)

* Replacement: change state in way method.

* State change is also needed when miss occurs, otherwise we will choose
a way that has been just refilled into cache as the victim.

* Optimize ctrlblock timing (#620)

* CtrlBlock: delay exception flush for 1 cycle

* CtrlBlock: delay load replay for 1 cycle

* roq: delay wb from exu for one clock cycle to meet timing

* CtrlBlock: fix pipeline bug between decode and rename

Co-authored-by: Yinan Xu <[email protected]>

* L1plusCache: use plru replacement policy.

* ICache: fix mmio bugs

1. MMIO cut helper uses packet align logic
2. still send req to uncache when flush

* ICache: change packet from mmio

use packet align as the mem

* IntrUncache: fix state bug

state will change into s_invalid and get stuck

* fix Registers that not being initiated

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update sc implementation, with wrbypass fixed in tage, bim and sc (#624)

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim:

update sc implementation, with wrbypass fixed in tage, bim and sc (#624)

* core: enable sc

* sc: calculate sum again on update

* sc: clean ups

* sc: add some debug info

* sc, tage, bim: fix wrbypass logic, add wrbypass for SC

* core: disable sc by default

Co-authored-by: jinyue110 <[email protected]>

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