fix(DFT): fix `DFT` cgen connection (#4565)

refactor(DFT): refactor `DFT` IO (#4530)

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=

feat(Sram): add `SRAM_CTL` interface (#4474)

* add `SRAM_CTL` interface for SRAMTemplate
* use `SRAM_WITH_CTL` to enable,
e.g. `make sim-verilog CONFIG=KunminghuV2Config RELEASE=1
SRAM_WITH_CTL=1`

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fix(PFEvent): use `CSRModule` for distribute_csr in PFEvent (#4321)

feat(dfx): integerate dfx components (#4312)

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI p

feat(bitmap/memenc): support memory isolation by bitmap checking and memory encrpty used SM4-XTS (#3980)

- Add bitmap module in MMU for memory isolation
- Add memory encryption module based on AXI protoco
- Can don't using these modules by setting the option `HasMEMencryption`
& `HasBitmapCheck` to false

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submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement fo

submodule(CoupledL2, OpenLLC): bump L2 and LLC (#4189)

This pull request includes:
- add compilation support for CHI Issue C (but not yet verified)
- enable DataCheck and Poison
- add requirement for CHI port width check
- add prefetch control by custom csr
- optimize timing in CoupledL2, mainly paths from SRAM to ICG
- add clock gate to each of the splitted SRAMs in CoupledL2
- fix several bugs concerning WriteEvictOrEvict, SnpQuery,
SnpCleanShared, SnpStash*, etc

---------

Co-authored-by: zhanglinjuan <[email protected]>
Co-authored-by: Ma-YX <[email protected]>
Co-authored-by: Yanqin Li <[email protected]>

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feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bo

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch
Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.

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feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check

feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check & ECC inject features
- Implement ICache ECC injection
- M-state software can write `eccctrl` to trigger error injection to meta/dataArray, next read can trigger auto-recovery (implemented in #3899)
- Remove custom CSR `Sfetchctl`

# Details
## CSR
The base address of the added mmio-mapped CSR is `0x38022080` and the registers is defined as below:
```
64 10 7 4 2 1 0
0x00 eccctrl | WARL | ierror | istatus | itarget | inject | enable |

64 PAddrBits-1 0
0x08 ecciaddr | WARL | paddr |
```
| CSR | field | desp |
| --- | --- | --- |
| eccctrl | enable | ECC check enable |
| eccctrl | inject | ECC inject enable (write 1 to trigger injection, read always 0) |
| eccctrl | itarget | ECC inject target<br>0: metaArray<br>1: rsvd<br>2: dataArray<br>3: rsvd |
| eccctrl | istatus | ECC inject status (read-only)<br>0: idle: inject controller idle, goes to working when received a inject request (i.e. write 1 to eccctrl.inject)<br>1: working: inject controller working, goes to injected when finished / error when failed<br>2: injected, goes to idle after read<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: error: inject failed (check eccctl.ierror for reason), goes to idle after read |
| eccctrl | ierror | ECC error reason (read-only, valid only if `eccctrl.istatus==error`)<br>0: ECC check is not enabled (i.e. `!eccctrl.enable`)<br>1: inject target invalid (i.e. `eccctrl.itarget==rsvd`)<br>2: inject addr (i.e. `ecciaddr.paddr`) not in ICache<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: rsvd |
| ecciaddr | paddr | Physical address of the inject target |

## Inject method
```asm
$INJECT_ADDR:
# maybe do something else
ret

test:
la t0, $BASE_ADDR # load icache control base addr
la t1, $INJECT_ADDR # load inject addr
jalr ra, 0(t1) # jump to injected addr to load it i
sd t1, 8(t0) # set inject addr
la t2, (target << 2 | 1 << 1 | 1 << 0) # load inject target & inject enable & ecc enable
sd t1, 0(t0) # set inject enable & ecc enable
loop:
ld t1, 0(t0) # get ecc control state
andi t1, t1, (0b11 << (4+1)) # get high bits of inject state
beqz t1, loop # if is idle, or working, loop

addi t1, t1, -1 # t1 = inject_state[2:1] - 1
bnez t1, error # if is not injected, error or rsvd

jalr ra, 0(t1) # jump to injected addr to trigger error
j finish

error:
# handle error
finish:
# finish
```
Or, checkout https://github.com/OpenXiangShan/nexus-am/pull/48

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feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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Frontend: modify the code related to configuration parameters (#3950)

fix(ICache,ITLB): also flush itlb pipe when prefetchPipe s1_flush (#3996)

ITLB does not store `gpaddr` to save resources, instead it takes
`gpaddr` from L2TLB when gpf occurs, which poses a two-opt

fix(ICache,ITLB): also flush itlb pipe when prefetchPipe s1_flush (#3996)

ITLB does not store `gpaddr` to save resources, instead it takes
`gpaddr` from L2TLB when gpf occurs, which poses a two-option
requirement for the requestor (i.e. IPrefetchPipe):
1. resend the same `itlb.io.req.vaddr` until `itlb.io.resp.miss` is
pulled down
2. flush gpf entry in ITLB by pulling up `itlb.io.flushPipe`

Otherwise, ITLB is unable to handle the next gpf and the core hangs.

However, the first point cannot be guaranteed during the speculative
execution, as IPrefetchPipe sends request to ITLB at s0 stage and may
receive a flush request from BPU s3 stage, IFU or Backend at s1 stage,
then the same vaddr is never resend to ITLB.

Therefore, we must ensure that ITLB is flushed synchronously when
IPrefetchPipe s1 stage is flushed, thus satisfying the second point.
This PR implements this.

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docs: add acknowledgements (#3861)

fix(CSR,RVC): c.fp instrs should be illegal when fs is off (#3859)

* fix RVC floating-point inst raise EX_II in predecode when xstatus.fs
is off

Fix #3864

Update: https://github.com/OpenXiang

fix(CSR,RVC): c.fp instrs should be illegal when fs is off (#3859)

* fix RVC floating-point inst raise EX_II in predecode when xstatus.fs
is off

Fix #3864

Update: https://github.com/OpenXiangShan/rocket-chip/pull/20 is merged
and this PR is rebased, ready to review.

---------

Co-authored-by: sinceforYy <[email protected]>

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style(frontend): manually wrap some line (#3791)

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

fix(BPU): remove reg of reset_vector (#3669)

feat: implement a new version of reset tree (#3546)

This commit uses `LazyRawModuleImp` to implement L2Top, MemBlock,
Backend and frontend so that when `--reset-gen` option is enabled, reset
input

feat: implement a new version of reset tree (#3546)

This commit uses `LazyRawModuleImp` to implement L2Top, MemBlock,
Backend and frontend so that when `--reset-gen` option is enabled, reset
input of these modules will go through `ResetGen` and then drives the
reset of the registers inside the module.

<img
src="https://github.com/user-attachments/assets/1f544afe-4644-4604-ba6f-d14d31909f78"
width="50%">

---------
Co-authored-by: chengguanghui <[email protected]>

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fix(frontend): fix simtime perf ctr frontendBubble

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded in

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded instruciton to IBuffer if the C extension 16 bits instruction is illegal.
* No need to use bypass illBuf, since the origin 16 bits instruction will be passed in the ctrlflow bundle.
* IBuffer
* Merge exceptionType and crossPageIPFFix into 3bit field, which type is IBufferExceptionType.
* IBufferExceptionType can hold illegal instruction exception.
* Backend
* CSROpType.ro is removed, since we can use rs1 and rd passed in imm field to distinguish CSRR and CSRW in CSR module.
* Create TrapInstMod to store the trap instruction and handle its update.

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Frontend: add RVC illegal instruction buffer

* Sstval requires instructions to be filled into stval

Frontend: implement prefetch.i support (RVA23 Zicbop) (#3396)

PcTargetMem: Fixed a bug that caused the backend to be unable to read the newest target (#3269)

CSR: remove useless distributedUpdate

frontend: io.fencei timing, add 1 cycle (#3238)