feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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fix(IFU): handle uncache corrupt (#4301)

When InstrUncache Tilelink bus gives `d.bits.corrupt` or `d.bits.denied`
(included in `d.bits.corrupt`), mark the fetch block as `access fault`,
and skips `m

fix(IFU): handle uncache corrupt (#4301)

When InstrUncache Tilelink bus gives `d.bits.corrupt` or `d.bits.denied`
(included in `d.bits.corrupt`), mark the fetch block as `access fault`,
and skips `m_resendTLB` etc..

Also:
- remove `currentIsRVC` as it's actually identical with `mmio_is_RVC`
- fix `crossPageIPFFix`, it should be valid only when `mmio_has_resend`
- rename `mmio_resend_exception` to `mmio_exception`, since it's also
used to store Tilelink corrupt before resend

Update: rebased to Feb-28-2025-66e9b546 for regression test.

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fix(exception): width of exception type should be explicitly noted (#4124)

refactor(IFU,ICache): refactor interface (#3914)

Move Vec(2) inside `ICacheMainPipeResp` to eliminate unused ports. No
functional changes.

refactor(Frontend): add ExceptionType.hasExcaption wrapper (#3866)

https://github.com/OpenXiangShan/XiangShan/pull/3787#discussion_r1818322915

fix(ICache): cancel prefetch when there is exception from backend (#3787)

style(frontend): manually wrap some line (#3791)

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

feat(ifu,ibuf): add isLastInFtqEntry in IBuffer

fix(BPU): adjust s3 target when fallThroughErr signal is high (#3636)

1. adjust S3 target address selection.

fix(ghist): fix ghist maintaining (#3635)

shouldShiftVec should be all zero when not hit


Related issue:

<img width="1243" alt="Screenshot 2024-09-23 at 21 25 07"
src="https://github.com/use

fix(ghist): fix ghist maintaining (#3635)

shouldShiftVec should be all zero when not hit


Related issue:

<img width="1243" alt="Screenshot 2024-09-23 at 21 25 07"
src="https://github.com/user-attachments/assets/28b94bb8-a9bb-43d9-927c-31c269adb60f">

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fix(BPU): adjust fallThroughErr signal usage strategy (#3627)

fix(BPU): modify the usage of the fallThroughErr signal (#3610)

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

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Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded in

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded instruciton to IBuffer if the C extension 16 bits instruction is illegal.
* No need to use bypass illBuf, since the origin 16 bits instruction will be passed in the ctrlflow bundle.
* IBuffer
* Merge exceptionType and crossPageIPFFix into 3bit field, which type is IBufferExceptionType.
* IBufferExceptionType can hold illegal instruction exception.
* Backend
* CSROpType.ro is removed, since we can use rs1 and rd passed in imm field to distinguish CSRR and CSRW in CSR module.
* Create TrapInstMod to store the trap instruction and handle its update.

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Trigger: refactor trigger information in pipeline. (#3403)

ICache: raise af if meta/data array ECC fail

In current design, meta/data array corruption does not raise any
exception (whether or not `io.csr_parity_enable === true.B`), which may
pose two probl

ICache: raise af if meta/data array ECC fail

In current design, meta/data array corruption does not raise any
exception (whether or not `io.csr_parity_enable === true.B`), which may
pose two problems:
1. When meta corrupt, `ptag` comparison result may be invalid, and thus
cache hit may be treated as a cache miss, thereby sending (pre)fetch
request to L2 cache incorrectly;
2. When meta/data/l2 corrupt, instruction data sent to the backend may
be invalid. Although the errors are sent to beu, which sends an
interrupt via plic, the timing of the interrupt is not as controllable
as an exception. It is therefore reasonable to mark invalid data as
access fault to keep it from execution.

This PR:
1. Raise af if meta/data array ECC fail (when `io.csr_parity_enable ===
true.B`), the priority of this af is lower than iTLB & PMP exceptions
2. Cancle (pre)fetching if meta array ECC fail (by merging
`meta_corrupt` exceptions to `s2_exception`)

Note:
RISC-V Machine ISA v1.13 (draft) introduced a "hardware error"
exception, described as:
> A Hardware Error exception is a synchronous exception triggered when
corrupted or uncorrectable data is accessed explicitly or implicitly by
an instruction. In this context, "data" encompasses all types of
information used within a RISC-V hart. Upon a hardware error exception,
the xepc register is set to the address of the instruction that
attempted to access corrupted data, while the xtval register is set
either to 0 or to the virtual address of an instruction fetch, load, or
store that attempted to access corrupted data. The priority of Hardware
Error exception is implementation-defined, but any given occurrence is
generally expected to be recognized at the point in the overall priority
order at which the hardware error is discovered.

Maybe it's better to raise hardware error instead of access fault when
ECC check failed. But it's draft and XiangShan backend does not
implement this exception code yet, so we still raise af here. This may
need to be modified in the future.

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Frontend: refactor exceptions to labels (#3354)

Combine `excp_pf`/`_gpf`/`_af` into `exception` to:
1. Reduce code redundancy and improve readability and maintainability
e.g. `!itlb_excp_af && !it

Frontend: refactor exceptions to labels (#3354)

Combine `excp_pf`/`_gpf`/`_af` into `exception` to:
1. Reduce code redundancy and improve readability and maintainability
e.g. `!itlb_excp_af && !itlb_excp_pf && !itlb_excp_gpf && !pmp_excp_af
&& !pmp_excp_mmio`
-> `exception === ExcedptionType.none && !mmio`
2. Select exceptions as they are generated (e.g. from iTLB/PMP, or
data/meta array ECC check) on a priority basis (e.g. iTLB over PMP),
ensuring that there is at most one exception in the pipeline (and on the
ports of iCache -> IFU)
3. Save a little bit of pipeline/WayLookup registers (i.e. 3 bit
`excp_pf`/`_gpf`/`_af` -> 2bit `exception`)

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build: purge chisel 3 and add deprecation check (#3250)

refactor: change exception encoding from one-hot to label (#3104)

ICache: implement new ICache (#3051)

Co-authored-by: xu_zh <[email protected]>

bpu: disable ittage when no indirect branch & ittage backward shift (#3092)

Co-authored-by: Easton Man <[email protected]>

FTB: Merge ftb low power & fix fallThroughAddr calculation. (#2997)

ftq: cut area of ftq_redirect_mem (#2856)

dlt folded_hist/afhob/lastBrNumOH
ftq_redirect_mem: 247*64->73*64

ftq: cut ftq area (#2806)

ftb_entry_mem:
full ftb_entry: reg->sram;
origin reg: dlt valid/lower/tarStat/pftAddr/carry/last_may_be_rvi_call/always_taken

ftq_meta_1r_sram:
dlt Tage_SC: sc

ftq: cut ftq area (#2806)

ftb_entry_mem:
full ftb_entry: reg->sram;
origin reg: dlt valid/lower/tarStat/pftAddr/carry/last_may_be_rvi_call/always_taken

ftq_meta_1r_sram:
dlt Tage_SC: scMeta-tageTakens/scUsed/providerResps-unconf/altDiffers/takens;
dlt ITTage: altDiffers/taken
dlt uFTB: pred_way
dlt RAS: sctr/TOSR/NOS

ftq_redirect_sram->ftq_redirect_mem

Co-authored-by: chenguokai <[email protected]>

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