feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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fix(TopDown, frontend): remove frontBubble double count on redirect (#4196)

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bo

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch
Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.

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feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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fix(ICache): cancel prefetch when there is exception from backend (#3787)

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

feat(ifu,ibuf): add isLastInFtqEntry in IBuffer

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

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fix(frontend): update Front_Bubble pmu

ibuffer deq signal had changed recently, this commit update the
pmu definition accordingly.

IBuffer: the priority of illegal instruction should be lower than fetch exception

* This commit fix the priorities between EX_II and other fetch exceptions in exception type transfer in IBuffer.
* T

IBuffer: the priority of illegal instruction should be lower than fetch exception

* This commit fix the priorities between EX_II and other fetch exceptions in exception type transfer in IBuffer.
* The fetch exceptions always have higher priority than EX_II. For example, when instruction access fault occurs, there will be not valid instruction.

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Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded in

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded instruciton to IBuffer if the C extension 16 bits instruction is illegal.
* No need to use bypass illBuf, since the origin 16 bits instruction will be passed in the ctrlflow bundle.
* IBuffer
* Merge exceptionType and crossPageIPFFix into 3bit field, which type is IBufferExceptionType.
* IBufferExceptionType can hold illegal instruction exception.
* Backend
* CSROpType.ro is removed, since we can use rs1 and rd passed in imm field to distinguish CSRR and CSRW in CSR module.
* Create TrapInstMod to store the trap instruction and handle its update.

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Trigger: refactor trigger information in pipeline. (#3403)

Frontend: refactor exceptions to labels (#3354)

Combine `excp_pf`/`_gpf`/`_af` into `exception` to:
1. Reduce code redundancy and improve readability and maintainability
e.g. `!itlb_excp_af && !it

Frontend: refactor exceptions to labels (#3354)

Combine `excp_pf`/`_gpf`/`_af` into `exception` to:
1. Reduce code redundancy and improve readability and maintainability
e.g. `!itlb_excp_af && !itlb_excp_pf && !itlb_excp_gpf && !pmp_excp_af
&& !pmp_excp_mmio`
-> `exception === ExcedptionType.none && !mmio`
2. Select exceptions as they are generated (e.g. from iTLB/PMP, or
data/meta array ECC check) on a priority basis (e.g. iTLB over PMP),
ensuring that there is at most one exception in the pipeline (and on the
ports of iCache -> IFU)
3. Save a little bit of pipeline/WayLookup registers (i.e. 3 bit
`excp_pf`/`_gpf`/`_af` -> 2bit `exception`)

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IBuffer: change read ptr logic for fix timing, change outputEntries logic for better performance

Decode and Ibuffer: change decodeCanAccept and bypass logic for fix timing

refactor: change exception encoding from one-hot to label (#3104)

IBuffer: fix a bypass bug when decode stage can not accept all the bypass insts (#2985)

IFU & GPAMem, RVH: fix the bug about getting gpa (#2960)

1. Delete some useless codes about gpaddr.
2. fix the bugs about wrong gpa was writen in mtval2 or htval when guest
page fault occured

IBuffer: consider valid signal in XSError (#2921)

Merge remote-tracking branch 'upstream/master' into tmp-master

Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

Ibuffer, PreDecode: consider valids for assertions (#2871)

RVH: finish the desigh of H extention

IBuffer: fix the update of deqPtrNext and deqBankPtrVecNext

* The update of deqPtrNext and deqBankPtrVecNext need not decodeCanAccept, since decode.io.in.ready may from complexDecoder

Decode,IBuffer: fix circle dependency deadlock

* Add a new field `canAccept` passed from decode to notice `IBuffer` that it can deq new instructions.
* IBuffer.io.out(i).ready depends on IBuffer.io.

Decode,IBuffer: fix circle dependency deadlock

* Add a new field `canAccept` passed from decode to notice `IBuffer` that it can deq new instructions.
* IBuffer.io.out(i).ready depends on IBuffer.io.out(i).ready.
* Since decode promises accepting insts in order, priority encoder is used to simplify the accumulation of `numDeq`.
* `numDeq` records the number of deq insts from ibuffer, not from bypass. And it is used to update deqPtr and corresponding deqBankPtr.
* Guard numFromFetch calculation with io.in.valid to avoid updating enqPtr when input signal is invalid.
* Todo: check ibuffer timing, critical path maybe ibuffer.io.out.valid -> ibuffer.io.out.ready -> ibuffer.validEntries -> nextValidEntries -> allowEnq

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