feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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fix(IFU): handle uncache corrupt (#4301)

When InstrUncache Tilelink bus gives `d.bits.corrupt` or `d.bits.denied`
(included in `d.bits.corrupt`), mark the fetch block as `access fault`,
and skips `m

fix(IFU): handle uncache corrupt (#4301)

When InstrUncache Tilelink bus gives `d.bits.corrupt` or `d.bits.denied`
(included in `d.bits.corrupt`), mark the fetch block as `access fault`,
and skips `m_resendTLB` etc..

Also:
- remove `currentIsRVC` as it's actually identical with `mmio_is_RVC`
- fix `crossPageIPFFix`, it should be valid only when `mmio_has_resend`
- rename `mmio_resend_exception` to `mmio_exception`, since it's also
used to store Tilelink corrupt before resend

Update: rebased to Feb-28-2025-66e9b546 for regression test.

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fix(IFU): add range checking for instruction blocks containing jalr (#4234)

When there is a jalr instruction in the middle of an instruction block
but
the BPU fails to predict it, the IFU should a

fix(IFU): add range checking for instruction blocks containing jalr (#4234)

When there is a jalr instruction in the middle of an instruction block
but
the BPU fails to predict it, the IFU should adjust the length of the
instruction block to terminate at the jalr instruction.
However, the IFU currently does not check for this scenario, which may
result in the unintended execution of instructions following the jalr
that
should not have been executed. This PR fixed this issue.

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fix(IFU): remove useless bpu override flush logic (#4210)

When an override occurs in BPU S3 stage, the corresponding req can at
most reach the IFU F0 stage.

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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Frontend: modify the code related to configuration parameters (#3950)

feat(IFU,Svpbmt): allow speculative fetch in pbmt.NC (idempotent) spaces (#3944)

Skip `m_waitLastCmt` & `m_waitCommit` state if `f3_itlb_pbmt ===
Pbmt.nc`, as these memory spaces are idempotent and

feat(IFU,Svpbmt): allow speculative fetch in pbmt.NC (idempotent) spaces (#3944)

Skip `m_waitLastCmt` & `m_waitCommit` state if `f3_itlb_pbmt ===
Pbmt.nc`, as these memory spaces are idempotent and in which we can do
speculative inst fetch.

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fix(IFU): mark mmio mismatch exception only on the second line (#3963)

When mmio mismatch happens, we can still fetch inst from the first page.
So we can just mark the exception on the second cache

fix(IFU): mark mmio mismatch exception only on the second line (#3963)

When mmio mismatch happens, we can still fetch inst from the first page.
So we can just mark the exception on the second cacheline.

Also fixes a bug: when itlb page fault occurs only on the second page,
PMP check may return incorrect results (as the input paddr may be
incorrect), on which request the mmio mismatch check should not be
performed. (Here we still perform the check, but the result will be
ignored, since itlb exception has higher priority in
`ExceptionType.merge`)

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refactor(IFU,ICache): refactor interface (#3914)

Move Vec(2) inside `ICacheMainPipeResp` to eliminate unused ports. No
functional changes.

fix(CSR): correct the width of PC pgaddr for inst fetch exception (#3795)

We found that the CSR mtval2 truncates the high bits of gpaddr when GPF
occurs in instruction fetching. Actually, there is

fix(CSR): correct the width of PC pgaddr for inst fetch exception (#3795)

We found that the CSR mtval2 truncates the high bits of gpaddr when GPF
occurs in instruction fetching. Actually, there is an GPAMem which
storages the whole 64-bit gpaddr, but it does not pass to CSR correctly,
due to incorrect width of trapPCGPA in module NewCSR and bundle
TrapEntryEventInput. This patch fixes this.

---------

Co-authored-by: ngc7331 <[email protected]>

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docs(IFU): add comments to a frequently asked `Cat` (#3874)

fix(IFU): check consistency of mmio states (#3873)

Should raise access fault when:
1. Inconsistent mmio states for two cachelines of a double-line request.
2. Inconsistent mmio states with ICache

fix(IFU): check consistency of mmio states (#3873)

Should raise access fault when:
1. Inconsistent mmio states for two cachelines of a double-line request.
2. Inconsistent mmio states with ICache check result when IFU mmio fsm
rechecks itlb/pmp.

"mmio state" here refers to `pmp.io.resp.mmio` and/or
`itlb.io.resp.pbmt`.

In current design:
1. When the mmio states of the two cachelines do not match, we fetch the
instructions according to the state of the first cacheline. This can
result in instructions in mmio space being cached by ICache
(functionality error), or doing uncache fetch in non-mmio space
(performance loss).
2. IFU mmio fsm only re-checks the response of PMP, which is incorrect
after the introduction of the Svpbmt extension (should allow for the
case where `pmp.io.resp.mmio === false.B` and
`Pbmt.isUncache(itlb.io.resp.pbmt)`, not an access fault in this case).

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refactor(Frontend): add ExceptionType.hasExcaption wrapper (#3866)

https://github.com/OpenXiangShan/XiangShan/pull/3787#discussion_r1818322915

fix(CSR,RVC): c.fp instrs should be illegal when fs is off (#3859)

* fix RVC floating-point inst raise EX_II in predecode when xstatus.fs
is off

Fix #3864

Update: https://github.com/OpenXiang

fix(CSR,RVC): c.fp instrs should be illegal when fs is off (#3859)

* fix RVC floating-point inst raise EX_II in predecode when xstatus.fs
is off

Fix #3864

Update: https://github.com/OpenXiangShan/rocket-chip/pull/20 is merged
and this PR is rebased, ready to review.

---------

Co-authored-by: sinceforYy <[email protected]>

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fix(ICache): cancel prefetch when there is exception from backend (#3787)

style(frontend): manually wrap some line (#3791)

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

docs(ifu): add comment about isLastInFtqEntry gen

feat(ifu,ibuf): add isLastInFtqEntry in IBuffer

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condi

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condition is
not satisfied for prefetch and redirected requests, resulting in stuck.
This commit fixes this bug.

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feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump

fix(exception): check high address bits of jump target (#3003)

This commit contains high address bits checking of jump target. In
previous implementation, we simply truncated the higher bits of jump
target address, which made it impossible to raise exceptions in such
cases.

To resolve this problem, we detect the invalid jump target in
jump/branch/CSR and, this information to frontend and store the complete
invalid target in a single register in backend. The frontend will then
raise an exception to backend and backend will also use the invalid
target in the register to write xtval and mepc.

---------

Co-authored-by: Muzi <[email protected]>
Co-authored-by: ngc7331 <[email protected]>

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IFU: fix RVCExpander of inst from mmio

* This commit fix the expansion of inst from mmio.
* The inst from mmio should behave the same as the insts from cache.

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded in

Frontend,Backend: add xxtvala support

* utils
* Add checkInputWidth function in NamedUInt to check if the UInt arg passed in has the same width as it defined.
* Frontend
* Pass the unexpanded instruciton to IBuffer if the C extension 16 bits instruction is illegal.
* No need to use bypass illBuf, since the origin 16 bits instruction will be passed in the ctrlflow bundle.
* IBuffer
* Merge exceptionType and crossPageIPFFix into 3bit field, which type is IBufferExceptionType.
* IBufferExceptionType can hold illegal instruction exception.
* Backend
* CSROpType.ro is removed, since we can use rs1 and rd passed in imm field to distinguish CSRR and CSRW in CSR module.
* Create TrapInstMod to store the trap instruction and handle its update.

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