style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

New RAS design (#2292)

By introducing non-volatile queue for specutive states, RAS avoids entry pollution

Co-authored-by: Easton Man <[email protected]>

bpu: duplicate most possible signal related to npc generation to address (#2254)

high fanout problems

Co-authored-by: Lingrui98 <[email protected]>

RAS: fix uninitialized top and write bypass entry (#2250)

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

bpu: add reset back

ras: initialize write_bypass_valid to deal with unexpectable x states

bpu: refactor prediction i/o bundles

bpu: refactor BranchPredictionUpdate bundle

Previously the BranchPredictionUpdate bundle was inherited from
BranchPredictionBundle, and that made some field of the bundle
unused. It was hard to find

bpu: refactor BranchPredictionUpdate bundle

Previously the BranchPredictionUpdate bundle was inherited from
BranchPredictionBundle, and that made some field of the bundle
unused. It was hard to find which signals are really in use.
Now we make BranchPredictionUpdate a independent bundle, so that
the signals in it are all in use.

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bpu: remove most reset signals of SRAMs

ras: delay write for 1 cycle and bypass write to read

bpu: bring bpu control signals into use (#1477)

ftb,ftq: add a bit indicating there is an rvi call at the last 2 byte for ras to push the right address

ras: should not push or pop when s3_redirect

tage: improve performance and reduce area

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch pre

tage: improve performance and reduce area

* split entries into by numBr and use bits in pc to hash between them
* use shorter tags for each table
* make perfEvents a general interface for branch predictor components
in order to remove casting operation in composer

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ras: let counters use zero value after first push

ras: fix a really stupid bug

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* le

bpu: timing optimizations

* move statisical corrector to stage 3
* add recover path in stage 3 for ras in case stage 2 falsely push or pop
* let stage 2 has the highest physical priority in bpu
* left ras broken for the next commit to fix

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bpu: try to avoid making some invalid predictions that occupy cache bandwidth

* block reads when ittage writes
* reset ras on reset so that it would not provide random addresses

ubtb: refactor prediction mechanism(temp commit)

bpu: timing optimizations

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce lo

bpu: timing optimizations

* use parallel mux to select provider and altprovider for TAGE and ITTAGE
* reduce logics on SC prediction
* calculate higher bits of targets at stage 1 for ftb
* reduce logics for RAS and ITTAGE prediction assignment

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bpu: remove stage 3

bpu: timing optimizations

* let ubtb store full targets and fall through addresses
* add some fields in BranchPrediction so that ifu requests can be solely derived from it