feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)

Hello, this change set is to remove the SRAM read-write conflict
handling logic in the frontend, after OpenXiangShan/Uti

feat: move frontend SRAM read-write conflict handling to SRAMTemplate (#4445)

Hello, this change set is to remove the SRAM read-write conflict
handling logic in the frontend, after OpenXiangShan/Utility#110 has been
merged, which adds this logic to the SRAMTemplate. See that pull request
and also #4242 for more context.

After this change, I see microbench IPC change 1.397 -> 1.413 and
coremark IPC change 2.136 -> 2.147. The branch mispredictions also
decreased slightly in both.

This probably cannot be merged automatically, since the utility
submodule should point to the new revision after merging instead of the
revision in my branch.

Thanks, Sam

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style(frontend): manually wrap some line (#3791)

style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

fix(tage): tage bt sram read and write the same addr at the same time (#3606)

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

bpu: add plru replacer to WrBypass (#2050)

* bpu: add plru replacer in wrbypass

also remove tag in Tage and ITTage wrbypass

* tage: fix idx width

* bpu: wrbypass cleanup and add comments a

bpu: add plru replacer to WrBypass (#2050)

* bpu: add plru replacer in wrbypass

also remove tag in Tage and ITTage wrbypass

* tage: fix idx width

* bpu: wrbypass cleanup and add comments about shared replacer

* bpu: fix code style

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Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

wrbypass: add initial state registers to address x state problems

Bump chisel to 3.5.0

wrbypass: use CAM to store idx and tag and use Mem to store data

bpu: extract wrbypass to be a module