feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check

feat(ICache): ECC error injection (#4044)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)* error recovery features.

- Add a series of mmio-mapped CSR to control ICache ECC check & ECC inject features
- Implement ICache ECC injection
- M-state software can write `eccctrl` to trigger error injection to meta/dataArray, next read can trigger auto-recovery (implemented in #3899)
- Remove custom CSR `Sfetchctl`

# Details
## CSR
The base address of the added mmio-mapped CSR is `0x38022080` and the registers is defined as below:
```
64 10 7 4 2 1 0
0x00 eccctrl | WARL | ierror | istatus | itarget | inject | enable |

64 PAddrBits-1 0
0x08 ecciaddr | WARL | paddr |
```
| CSR | field | desp |
| --- | --- | --- |
| eccctrl | enable | ECC check enable |
| eccctrl | inject | ECC inject enable (write 1 to trigger injection, read always 0) |
| eccctrl | itarget | ECC inject target<br>0: metaArray<br>1: rsvd<br>2: dataArray<br>3: rsvd |
| eccctrl | istatus | ECC inject status (read-only)<br>0: idle: inject controller idle, goes to working when received a inject request (i.e. write 1 to eccctrl.inject)<br>1: working: inject controller working, goes to injected when finished / error when failed<br>2: injected, goes to idle after read<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: error: inject failed (check eccctl.ierror for reason), goes to idle after read |
| eccctrl | ierror | ECC error reason (read-only, valid only if `eccctrl.istatus==error`)<br>0: ECC check is not enabled (i.e. `!eccctrl.enable`)<br>1: inject target invalid (i.e. `eccctrl.itarget==rsvd`)<br>2: inject addr (i.e. `ecciaddr.paddr`) not in ICache<br>3: rsvd<br>4: rsvd<br>5: rsvd<br>6: rsvd<br>7: rsvd |
| ecciaddr | paddr | Physical address of the inject target |

## Inject method
```asm
$INJECT_ADDR:
# maybe do something else
ret

test:
la t0, $BASE_ADDR # load icache control base addr
la t1, $INJECT_ADDR # load inject addr
jalr ra, 0(t1) # jump to injected addr to load it i
sd t1, 8(t0) # set inject addr
la t2, (target << 2 | 1 << 1 | 1 << 0) # load inject target & inject enable & ecc enable
sd t1, 0(t0) # set inject enable & ecc enable
loop:
ld t1, 0(t0) # get ecc control state
andi t1, t1, (0b11 << (4+1)) # get high bits of inject state
beqz t1, loop # if is idle, or working, loop

addi t1, t1, -1 # t1 = inject_state[2:1] - 1
bnez t1, error # if is not injected, error or rsvd

jalr ra, 0(t1) # jump to injected addr to trigger error
j finish

error:
# handle error
finish:
# finish
```
Or, checkout https://github.com/OpenXiangShan/nexus-am/pull/48

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refactor(ICache): refactor code style & eliminate IDE warnings (#3947)

- add type annotation to public members
- add private qualifier to other members
- add `asUInt` to shift results (Bits)
- fi

refactor(ICache): refactor code style & eliminate IDE warnings (#3947)

- add type annotation to public members
- add private qualifier to other members
- add `asUInt` to shift results (Bits)
- fix typo
- remove unused imports
- rename `ICacheMSHR.waymask` to `way` since it is not a mask
- use `idxBits` for `log2Up(nSets)`
- use `wayBits` for `log2Up(nWays)`
- use `foreach` instead of `map` when return value is not needed
- use `{}` instead of `()` for multi-line `foreach` and `map`

The generated verilog is checked and is identical with the original
(except `waymask` -> `way` & order changes).

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feat(ICache): re-fetch data from L2 if ECC error is detected (#3899)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)*
error recovery features.

Unlike DCache, data in ICache i

feat(ICache): re-fetch data from L2 if ECC error is detected (#3899)

This PR is part of *RAS(Reliability, Accessibility, Serviceability)*
error recovery features.

Unlike DCache, data in ICache is always not dirty, so when it is
corrupted, we can always re-fetch from L2 cache.

Port & behavior changes:
- Add a `flush` port to metaArray, letting mainPipe be able to clear
valid_array before doing re-fetch, thereby preventing multi-hit in
ICache.
- if metaArray ECC error is detected, flush vSets in each way, since
`waymask` is unreliable.
- if dataArray ECC error is detected, flush the vSet in way specified by
`waymask`.
- metaArray / dataArray ECC errors will no longer raise access fault, as
they can be resolved by re-fetching. Raise af only when response from L2
is marked as corrupted.
- When ECC error is detected, mainPipe will send miss requests to L2
through MissUnit.

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style(Frontend): use scalafmt formatting frontend (#3370)

Format frontend according to the scalafmt file drafted in #3061.

ICache: fix metaArray ECC check (#3419)

Currently, metaArray ECC check is valid 2 cycles after request:

https://github.com/OpenXiangShan/XiangShan/blob/49162c9ab67070931573c1d4a372e2c858a72716/sr

ICache: fix metaArray ECC check (#3419)

Currently, metaArray ECC check is valid 2 cycles after request:

https://github.com/OpenXiangShan/XiangShan/blob/49162c9ab67070931573c1d4a372e2c858a72716/src/main/scala/xiangshan/frontend/icache/ICache.scala#L262

However, prefetchPipe s1 handshakes with both WayLookup and prefetchPipe
s2 assuming that all signals of the metaArray.io.readResp are valid 1
cycle after the request, resulting in the error.

Simply removing this RegEnable may lead to problems with long timing
paths (metaArray (sram) -> ECC check (xor reduction) -> prefetchPipe s1
(wire) -> wayLookup (bypass, wire) -> mainPipe s0 (wire) -> mainPipe s1
(reg)), so no.

This PR may result in case-specific errors not being checked out, which
in turn results in additional fetch requests being sent to the L2 cache,
but does not causes corrupted data being sent to the backend. See
discussion in notes:

https://github.com/OpenXiangShan/XiangShan/blob/8b87b8dcbfd5945c5bd7815eb5e569fec252ddc6/src/main/scala/xiangshan/frontend/icache/IPrefetch.scala#L279-L293

There are 2 more potential solutions described in an internal yuque
document, however, due to the complexity of implementation, area
overhead and other considerations, the current solution is considered to
be optimal.

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build: purge chisel 3 and add deprecation check (#3250)

ICache: implement new ICache (#3051)

Co-authored-by: xu_zh <[email protected]>

ICache: split cacheline in mainPipe and dataArray (#2609)

fdip: change instruction prefetch position to L2 (#2320)

* fdip: change prefetchQueue structure from shiftReg to fifo
* icache: add perfAccumulate to statistics the latency distribution of MSHR

Bump rocket-chip (#2353)

icache: change itlb port to no-blocked and new fdip (#2277)

ICache: merge master

ICache：remove coherence & add fencei support (#2043)

* ICache:send Get instead of Acquire to L2

* ICache:add vaild_array in metaArray

* [WIP]ICache:annotate invalid coherence modules for icach

ICache：remove coherence & add fencei support (#2043)

* ICache:send Get instead of Acquire to L2

* ICache:add vaild_array in metaArray

* [WIP]ICache:annotate invalid coherence modules for icache

* ICache:delete invalid coherence modules for icache

* ICache : add fencei logic

* ICache : fix check multi-hit logic

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ICache:finish migrate fdip from branch <kmh-fdip>

ICache:delete invalid coherence modules for icache

[WIP]ICache:annotate invalid coherence modules for icache

ICache:add vaild_array in metaArray

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

<bug-fix>: fix port_1_read_0 condition

ICache: separate meta/data to 4 2-way banks

* add ICachPartWayArray to wrap a part-way module

* SRAM array array_0 array_1: width × 1/4 and depth stay unchanged

ICache: add difftest-Refill test (#1548)

ICache <timing>: move parity decode to pipeline (#1443)

* ICache <timing>: move parity decode to pipe

* ICacheMainPipe <timing>: remove parity af

* ReplacePipe <timing>: delay error generating

ICache: raise AF exception when parity wrong or L2 send corrupt (#1376)

* ICache: raise access fault when L2 send corrupt

* ICache: add ECC error connection

* chores: add comments and code cle

ICache: raise AF exception when parity wrong or L2 send corrupt (#1376)

* ICache: raise access fault when L2 send corrupt

* ICache: add ECC error connection

* chores: add comments and code clean-up

* ICache: raise AF when Meta/Data Parity wrong

* Update Frontend.scala

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Optimize IFU and PreDecode timing (#1347)

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfi

Optimize IFU and PreDecode timing (#1347)

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfig

* TODO: set conflict for ReplacePipe

* ICache: fix ReplacePipe invalid write bug

* chores: code clean up

* IFU: optimize timing

* PreDecode: separate into 2 module for timing optimization

* IBuffer: add enqEnable to replace valid for timing

* IFU/ITLB: optimize timing

* IFU: calculate cut_ptr in f1

* TLB: send req in f1 and wait resp in f2

* ICacheMainPipe: add tlb miss logic in s0

* Optimize IFU timing

* IFU: fix lastHalfRVI bug

* IFU: fix performance bug

* IFU: optimize MMIO commit timing

* IFU: optmize trigger timing and add frontendTrigger

* fix compile error

* IFU: fix mmio stuck bug

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ICache: add ReplacePipe for Probe and Release (#1303)

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on M

ICache: add ReplacePipe for Probe and Release (#1303)

* ICache: add ReplacePipe for Probe & Release

* remove ProbeUnit

* Probe & Release enter ReplacePipe

* fix bugs when running Linux on MinimalConfig

* TODO: set conflict for ReplacePipe

* ICache: add Block logic for ReplacePipe

* ReplacePipe: change probe assert condition

* support Probe NToN (Probe not hit in ICache)

* ICache: fix a bug in meta_write_arb

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