fix(LSU): misaligned violation detection stuck (#4369)

Since a load instruction that cross 16Byte needs to be split and
accessed twice, it needs to enter the `RAR Queue` twice, but occupies
only one

fix(LSU): misaligned violation detection stuck (#4369)

Since a load instruction that cross 16Byte needs to be split and
accessed twice, it needs to enter the `RAR Queue` twice, but occupies
only one `virtual load queue`, so in the extreme case it may happen that
36 load instructions that span 16Byte fill all 72 `RAR queues`.

---

There is some problem with our previous handling; if the oldest load
instruction spanning 16Byte enters the `replayqueue` and at the same
time there exists an instruction in the `loadmisalignbuffer` that can't
finish executing because the `RAR Queue` is full, then the oldest load
instruction is never cannot be issued because the `loadmisalignbuffer`
has instructions in it all the time.

---

Therefore, we use a more violent scheme to do this.
When the RAR is full, we let the misaligned load generate a rollback,
and the next load instruction that the loadmisalignbuffer can receive
must be the oldest (if it is misaligned).

show more ...

style(Bundles): move bundles to Bundles.scala (#4247)

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

show more ...

fix(LSQ): modify misaligned `forward fault` detection (#4038)

Previously, I used an inappropriate way for another misalign to trigger
a `forward fault`:


https://github.com/OpenXiangShan/XiangShan/

fix(LSQ): modify misaligned `forward fault` detection (#4038)

Previously, I used an inappropriate way for another misalign to trigger
a `forward fault`:


https://github.com/OpenXiangShan/XiangShan/blob/38d0d7c5a34a23dfdb58a3cb2737c3cfddb3ec9d/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala#L684-L711

This would cause the `BlockSqIdx` passed to `LoadQueueReplay` to use the
`sqIdx` from `uop` instead of the `sqIdx` with the unalign flag bit:

https://github.com/OpenXiangShan/XiangShan/blob/38d0d7c5a34a23dfdb58a3cb2737c3cfddb3ec9d/src/main/scala/xiangshan/mem/lsqueue/StoreQueue.scala#L776-L782

**This leads to a possible stuck in `LoadQueueReplay`.**

And to resolve the stuck, we incorrectly introduced this
Commit(af757d1b973e03dae3ce0078a4a8249b593188ec).

This Commit(af757d1b973e03dae3ce0078a4a8249b593188ec) causes
`BlockSqIdx` to unblock without `DataValid`.
This leads to certain performance issues.

This revision fixes the inappropriate `forward fault` triggering method
and reverses the Commit(af757d1b973e03dae3ce0078a4a8249b593188ec).

**This should bring performance back up again.**
### Apologies for my mistake.

show more ...

fix(LoadQueueReplay): more precise for unblocking `forwarding fault`

It is not necessary to check whether the storequeue entry pointed to by sqidx is complete, because this entry is the store that f

fix(LoadQueueReplay): more precise for unblocking `forwarding fault`

It is not necessary to check whether the storequeue entry pointed to by sqidx is complete, because this entry is the store that follows this load.

show more ...

feat(Zicclsm): refactoring misalign and support vector misalign

fix(LoadQueueReplay): fix enq mask generate when redirect (#3884)

* Bug descriptions:
When an instruction first enq LoadQueueReplay and needs to be
redirected, the EnqMask generation does not take

fix(LoadQueueReplay): fix enq mask generate when redirect (#3884)

* Bug descriptions:
When an instruction first enq LoadQueueReplay and needs to be
redirected, the EnqMask generation does not take this situation into
account, then incorrectly updating the age matrix.

* Bug fix
use newEnqueue to generate EnqMask

show more ...

area(MemBlock): remove redundant signals to optimise area (#3560)

optimise redundant signals to reduce MemBlock area.
1. optimise 'exceptionVec', selected by LduCfg or StaCfg;
2. optimise 'fuType'

area(MemBlock): remove redundant signals to optimise area (#3560)

optimise redundant signals to reduce MemBlock area.
1. optimise 'exceptionVec', selected by LduCfg or StaCfg;
2. optimise 'fuType', reassign the value when writeback Rob in pipeline,
so no longer saved in LSQ.
3. optimise 'uop.imm', vaddr is computed in StoreMisalignBuffer and
there is no need to store the uop.imm.

show more ...

fix(LoadQueueReplay): fix blocking logic (#3590)

LoadQueueReplay: fix LoadQueueReplay enqueue logic (#3436)

LoadQueueReplay can always enter, as long as it is the same size as
VirtualLoadQueue.

LSQ: optimize static clock gating coverage and fix x_value in vcs (#3176)

optimize LSQ static clock gating coverage, fix x_value in vcs

LoadQueueReplay: fix enq ready logic

Revert "LSQ: optimize static clock gating coverage (#3023)" (#3055)

LSQ: refactor vector load/store commit judging logic to fix X in vcs (#3048)

LSQ: optimize static clock gating coverage (#3023)

LoadqueueReplay: Entry should be allocated when matching mergebuffer feedback (#3010)

Merge branch 'master' into vlsu-merge-master-0504

Bump utility and disable ConstantIn by default (#2955)

* use BigInt for initValue of Constantin.createRecord
* use WITH_CONSTANTIN=1 to enable the ConstantIn plugin

Merge branch 'master' into vlsu-tmp-master

VLSU, lsq: support more than one vector pipeline

Memblock, LoadReplayQueue: fix bug of ageMatrix enq && deq

LoadReplayQueue: fix age matrix dequeue

VLSU: support of vector store/load exception

VLSU: add support that replay vector load mask

rv64v: implement lsu & lsq vector datapath

Merge remote-tracking branch 'upstream/master' into tmp-master