submodule(utility), XSDebug: support collecting missing XSDebug (#4251)

Previous in PR#3982, we support collecting XSLogs to LogPerfEndpoint.
However with --enable-log, we should also collect some

submodule(utility), XSDebug: support collecting missing XSDebug (#4251)

Previous in PR#3982, we support collecting XSLogs to LogPerfEndpoint.
However with --enable-log, we should also collect some missing XSDebug.

This change move these missing XSDebug outside WhenContext, and add
WireInit to LogUtils' apply, to enable probing some subaccessed data,
like a vec elem with dynamic index.

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style(Bundles): move bundles to Bundles.scala (#4247)

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bo

feat(TopDown): add TopDown PMU Events (#4122)

This PR adds hardware synthesizable three-level categorized TopDown
performance counters.
Level-1: Retiring, Frontend Bound, Bad Speculation, Backend Bound.
Level-2: Fetch Latency Bound, Fetch Bandwidth Bound, Branch
Missprediction, machine clears, Core Bound, Memory Bound.
Leval-3: L1 Bound, L2 Bound, L3 Bound, Mem Bound, Store Bound.

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fix(LSQ): fix 'enqCancelNum' bit width (#4109)

area(VirtualLoadQueue): remove useless regs (#4061)

* remove datavalid, addrvalid, veccommitted
* add committed

fix(MemBlock): fix overflow during lsqptr calculation (#4084)

The addition used previously to calculate the `lsq` pointer results in
overflow, this is because, the bit width of `numLsElem` is 5 and

fix(MemBlock): fix overflow during lsqptr calculation (#4084)

The addition used previously to calculate the `lsq` pointer results in
overflow, this is because, the bit width of `numLsElem` is 5 and
multiple uop accumulations result in data overflow.

---

Theoretically this would have been a problem in previous versions as
well, but for some reason the bug didn't occur in previous versions
until `newDispatch`.

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feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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fix(LSQ): modify the enq logic

This commit modifies the previous silly queue entry.
This greatly reduces the generated verilog, making:
StoreQueue verilog in StoreQueue from 26W lines -> 5W lines
ve

fix(LSQ): modify the enq logic

This commit modifies the previous silly queue entry.
This greatly reduces the generated verilog, making:
StoreQueue verilog in StoreQueue from 26W lines -> 5W lines
verilog in VirtualLoadQueue from 13W lines -> 2W lines

Also, we can no longer limit the number of numLsElem per `io.enq`.

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feat(Zicclsm): refactoring misalign and support vector misalign

area(MemBlock): remove redundant signals to optimize area (#3777)

feat(rv64v): support first only fault instruction

fix(LoadQueue): software prefetch should always be ready to deq (#3484)

A software prefetch instruction is similar to a normal load instruction
in that it allocates loadqueue entries, and we need t

fix(LoadQueue): software prefetch should always be ready to deq (#3484)

A software prefetch instruction is similar to a normal load instruction
in that it allocates loadqueue entries, and we need to write them back
to the backend through loadunit. Unlike normal load instructions,
software prefetch instructions will not be replayed, and will be written
directly back to the backend. At the same time in loadqueue, as long as
this instruction is at the head of the queue, it can deq.

In the past design, although the software prefetch instruction will not
enter load replay queue, it still needs to wait for both addrvalid and
datavalid to be ready before it can deq from loadqueue, which in fact
will cause the entry to never deq from loadqueue, resulting in a
deadlock. This commit fixes this bug: addrvalid and datavalid will
always be considered true for software prefetch instructions.

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timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Opt

timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Optimize VLSU feedback and redirect
+ Optimise ldCancel and writeback signal generation
+ Optimise TLB Query Vaddr/hlv/hlvx/valid etc
+ Delay MMIO Store writeback for 1 Cycle
+ Fix tlbNoQuery and pmp logic
+ Remove clock gating for s3_fast_rep
+ Remove wbq conflict check to LoadPipe/MainPipe
+ Remove Mux in dcache resp data
+ Optimise data generation logic of LoadUnit
+ Duplicate Register in LoadUnit for data writeback
+ Duplicate Register in loadPipe for missQueue enq
+ Add skid buffer in VLSU
+ Select data from metaArray at S1
+ Simplify the enqueuing logic of missQueue
+ Separately generate the ready logic of miss Queue
+ Relax the conditions valid for bankdataArray reads
+ Add Reg between Dcache Mainpipe with sms prefetcher
+ Optimise store exceptionBuffer pipeline

---------

Co-authored-by: weiding liu <[email protected]>
Co-authored-by: Charlie Liu <[email protected]>
Co-authored-by: good-circle <[email protected]>

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LSQ: optimize static clock gating coverage and fix x_value in vcs (#3176)

optimize LSQ static clock gating coverage, fix x_value in vcs

build: purge chisel 3 and add deprecation check (#3250)

VLSU: Change the maximum number of 'numLsElem' dispatch by 'dispatch2iq'.

For emulation on Palladium, now the maximum 'numLsElem' number that can be emitted per port is:
16 2 2 2 2 2.

So vector i

VLSU: Change the maximum number of 'numLsElem' dispatch by 'dispatch2iq'.

For emulation on Palladium, now the maximum 'numLsElem' number that can be emitted per port is:
16 2 2 2 2 2.

So vector instructions other than 'unit-stride' can only be issued on the first port.
Scalars and 'unit-stride' instruction can be emitted at either port if the 'Lsq' allows allocation.

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VirtualLoadQueue: remove useless logic (#3066)

Revert "LSQ: optimize static clock gating coverage (#3023)" (#3055)

LSQ: refactor vector load/store commit judging logic to fix X in vcs (#3048)

LSQ: optimize static clock gating coverage (#3023)

VLSU, lsq: support more than one vector pipeline

Dispatch2Iq, package: make the encoding and decoding more standardized

VLSU, lsq: fix calcualte of enqptr when redirect

VLSU: Add performance counters and parameters

VLSU,LSQ: fix lqIdx/sqIdx calcualte when allocate entries