feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
Wh

feat(XSLog): move all XSLog outside WhenContext for collection

As data in WhenContext is not acessible in another module. To support
XSLog collection, we move all XSLog and related signal outside
WhenContext. For example, when(cond1){XSDebug(cond2, pable)} to
XSDebug(cond1 && cond2, pable)

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docs: add acknowledgements (#3861)

perf(ssit): allocate upon the first violation

Co-authored-by: weidingliu

Backend: add ren signal to SyncDataModuleTemplate

stIn: connect missing wire

Merge upstream/master into tmp-backend-merge-master

Bump rocket-chip (#2353)

chore: remove deprecated brackets, APIs, etc. (#2321)

fix s2_ldSsidAllocate/s2_stSsidAllocate (#2260)

s2_ldSsidAllocate and s2_stSsidAllocate used data from the last cycle (s1)

Merge remote-tracking branch 'upstream/master' into new-backend

backend: merge v2backend into backend

circt: fix assertion fails in circt simulation (#2023)

backend: add load inst support

v2backend: huge tmp commit

Separate Utility submodule from XiangShan (#1861)

* misc: add utility submodule

* misc: adjust to new utility framework

* bump utility: revert resetgen

* bump huancun

Fix the mdp predicts that the load may depend on itself

mdp: fix wrong reset logic

mdp: check valid when redirect

This does not affect functionality. Only to avoid x-prop.

mdp: update validVec only when StoreSetHit

storeset: don't allocate upon the first violation (#1132)

This commit changes the allocation policy in Store Set memory
dependence predictor.

Previously we allocate an entry for the load and sto

storeset: don't allocate upon the first violation (#1132)

This commit changes the allocation policy in Store Set memory
dependence predictor.

Previously we allocate an entry for the load and store instructions
every time when a memory violation is triggered. However, it's not
robust enough and causes many load instructions to be blocked for
issuing.

The current allocation policy only allocates the same entry for the load
and store instructions after both of them have triggered memory
violations before. That is to say, only when a load/store instruction
pair triggers memory violation twice, we do allocate the same entry to
them. This change may cause more memory violation redirections than
before, but it also reduces the number of blocked load instructions.

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ssit: pipeline update logic to reduce fanin (#1583)

fix for chipsalliance/chisel3#2496 (#1563)

mdp: fix valid_sram write assertion (#1306)

storeset: fix SyncDataModuleTemplate assertion (#1297)

mem,mdp: use robIdx instead of sqIdx (#1242)

* mdp: implement SSIT with sram

* mdp: use robIdx instead of sqIdx

Dispatch refactor moves lsq enq to dispatch2, as a result, mdp can not
get corr

mem,mdp: use robIdx instead of sqIdx (#1242)

* mdp: implement SSIT with sram

* mdp: use robIdx instead of sqIdx

Dispatch refactor moves lsq enq to dispatch2, as a result, mdp can not
get correct sqIdx in dispatch. Unlike robIdx, it is hard to maintain a
"speculatively assigned" sqIdx, as it is hard to track store insts in
dispatch queue. Yet we can still use "speculatively assigned" robIdx
for memory dependency predictor.

For now, memory dependency predictor uses "speculatively assigned"
robIdx to track inflight store.

However, sqIdx is still used to track those store which's addr is valid
but data it not valid. When load insts try to get forward data from
those store, load insts will get that store's sqIdx and wait in RS.
They will not waken until store data with that sqIdx is issued.

* mdp: add track robIdx recover logic

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