fix(StoreUnit): cbo violation check should check cacheline (#4592)

The cbo instruction should check for violations at the granularity of
cacheline.

Theoretically modifying the condition of this var

fix(StoreUnit): cbo violation check should check cacheline (#4592)

The cbo instruction should check for violations at the granularity of
cacheline.

Theoretically modifying the condition of this variable would allow
checking at cacheline granularity in RAW and should not introduce any
other side effects.

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fix(LSU): misalign writeback aligned raw rollback (#4476)

By convention, we need to make `rollback` and `writeback` happen at the
same time, and not make `writeback` earlier than `rollback`.

Curren

fix(LSU): misalign writeback aligned raw rollback (#4476)

By convention, we need to make `rollback` and `writeback` happen at the
same time, and not make `writeback` earlier than `rollback`.

Currently, the `rollback` generated by raw occurs at `s4`.
A normal store would take an extra N beats after the end of s3 (based on
the number of RAWQueue entries, which is now 1 beat), which is
equivalent to `writeback` at `s4`
And misaligned would `writeback` at `s2`, then `writeback` after
switching to `s_wb` state, which is equivalent to `writeback` at `s3`

---

This pr adjusts the misaligned `writeback` logic to align with the
`StoreUnit`.
At the same time, it unified the way to calculate the number of beats.

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fix(LSU): fix exception for misalign access to `nc` space (#4526)

For misaligned accesses, say if the access after the split goes to `nc`
space, then a misaligned exception should also be generated.

fix(LSU): fix exception for misalign access to `nc` space (#4526)

For misaligned accesses, say if the access after the split goes to `nc`
space, then a misaligned exception should also be generated.

Co-authored-by: Yanqin Li <[email protected]>

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timing(StoreMisalignBuffer): fix misalign buffer enq timing (#4493)

* a misalign store will enqueue misalign buffer at s1, and revoke if it
needs at s2

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument

feat: support inst lifetime trace (#4007)

PerfCCT(performance counter commit trace) is a Instruction-level
granularity perfCounter like GEM5
How to use this:
1. Make with "WITH_CHISELDB=1" argument
2. Run with "--dump-db --dump-select-db lifetime", then get the database
3. Instruction lifetime visualize run "python3 scripts/perfcct.py
"the-db-file-path" -p 1 -v | less"
4. Analysis script now is in XS-GEM5 repo, see
https://github.com/OpenXiangShan/GEM5/blob/xs-dev/util/ClockAnalysis.py

How it works:
1. Allocate one unique tag "seqNum" like GEM5 for each instruction at
fetch stage
2. Passing the "seqNum" in each pipeline
3. Recording perf data through the DPIC interface

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fix(StoreUnit): no uncache store misalign of mmio (#4441)

**Read this PR(https://github.com/OpenXiangShan/XiangShan/pull/4442)
from LoadUnit first.**

---

In addition to the above, `nc` has been ad

fix(StoreUnit): no uncache store misalign of mmio (#4441)

**Read this PR(https://github.com/OpenXiangShan/XiangShan/pull/4442)
from LoadUnit first.**

---

In addition to the above, `nc` has been added to the misalign checks as
well.

(https://github.com/OpenXiangShan/XiangShan/pull/4441/files#diff-cd162a95fcb65b10cf6ac087d3aac686ccb932ab4f5e270c0cfdb38437462b37L464-R471)

---

Currently, it is not to fully replace `s2_mmio` with
`s2_actually_uncache` due to inconsistencies in the way `nc` and `mmio`
are handled in the `StoreQueue`, so the original `s2_mmio` is still
retained.
Other than that, there is no longer a need for an additional
`s2_uncache`, as StoreUnit does not need to handle prefetching.

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timing(STU, StoreMisalignBuffer): adjust misalign buffer enq logic (#4254)

There is no exception misaligned store instruction enters the
misalignbuffer. Due to the exception timing difference genera

timing(STU, StoreMisalignBuffer): adjust misalign buffer enq logic (#4254)

There is no exception misaligned store instruction enters the
misalignbuffer. Due to the exception timing difference generated by the
`PMA`, the timing of the misalignbuffer rejection condition is bad
timing, which in turn leads to the bad timing of `feedback_slow.hit`.

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style(Bundles): rewrite bundles with new style (#4274)

fix(LSU): fix cbo instr exceptions and implementation (#4262)

1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly

fix(LSU): fix cbo instr exceptions and implementation (#4262)

1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly
5. Adding RAW checks to `cbo zero`.
6. Adding trigger(Debug Mode) checks to `cbo zero`.
7. Fixed several issues with the CBO instruction in NEMU.
----

In order not to create ambiguity with `io.mmioStout`, a new port of
`StoreQueue` is introduced for writeback `cbo zero` after flush sbuffer.
arbitration is performed in `MemBlock`, and currently, `cbo zero` has
higher priority by default.
`cbo zero` should not be writteback at the same time as `mmio`.

---
A check on `CacheLine` has been added to `RAWQueue` to ensure memory
consistency when executing `cbo zero`.
See this issues:https://github.com/OpenXiangShan/XiangShan/issues/4240
for specific issues.

---
The `cbo` instruction requires a trigger check.

---------

Co-authored-by: zhanglinjuan <[email protected]>

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style(Bundles): move bundles to Bundles.scala (#4247)

fix(StoreUnit): misaligned store need check `RAW` (#4228)

fix(LSU): fix misalign store exception logic (#4239)

fix(LSU): fix cbo instruction exception handling logic (#4215)

timing(LoadUnit, StoreUnit): remove redirect for out (#4207)

* remove useless cancel logic for writeback valid

fix(VLSU): fix vector exception writeback to 'MergeBuffer' logic (#4137)

Fixed the bug of abnormal signal loss when writing back.

Previously, we expected to compare only the ports of the writebacks

fix(VLSU): fix vector exception writeback to 'MergeBuffer' logic (#4137)

Fixed the bug of abnormal signal loss when writing back.

Previously, we expected to compare only the ports of the writebacks that
triggered the exception and pick the oldest.

But amazingly, I just realised that the implementation doesn't match the
annotation. The current implementation can be problematic in that if
the write-back port that did not have an exception is older, the port that
triggered the exception is not elected.

Use s3_exception to try to optimise timing.

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fix(StoreUnit): mmio should not be set when a page fault (#4104)

submodule(CoupledL2, OpenLLC): support pbmt in CHI scene (#4071)

* L1: deliver the NC and PMA signals of uncacheReq to L2
* L2: [support Svpbmt on CHI
MemAttr](https://github.com/OpenXiangShan/Coupl

submodule(CoupledL2, OpenLLC): support pbmt in CHI scene (#4071)

* L1: deliver the NC and PMA signals of uncacheReq to L2
* L2: [support Svpbmt on CHI
MemAttr](https://github.com/OpenXiangShan/CoupledL2/pull/273)
* LLC: [Non-cache requests are forwarded directly downstream without
entering the slice](https://github.com/OpenXiangShan/OpenLLC/pull/28)

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fix(MemBlock): fix misaligned exception and remove redundant reg from `SQ`

feat(Zicclsm): refactoring misalign and support vector misalign

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std

feat(MemBlock): add support for Zacas extension

fix(AtomicsUnit, MemBlock): fix loss of multiple stds

In the previous design, AtomicsUnit receives stds from StdExeUnit and
arbitrate at most one std uop for one cycle. This works fine on most of
the AMOs and LR/SC because they require only one std uop. However AMOCAS
requires at least two std uops, which may be issued from two separate
issue queues at the same time, leading to the loss of std uops.

This commit fixes this by taking all the outputs of the StdExeUnits into
account with arbitration logics.

fix(AtomicsUnit): DCache req can only be sent at `s_cache_req`

fix(AtomicsUnit, difftest): fix difftest io for atomic events

fix(MainPipe): fix precedence of `&` and `=/=` operator

fix(MainPipe): AMOCAS should not wait for AMOALU

fix(MemBlock): remove unnecessary assertion

fix(MainPipe): only CAS instruction can assert `s3_cas_fail`

fix(AtomicsUnit): fix bug in data select logic

submodule(difftest): bump difftest

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feat(pointer masking): support Ssnpm & Smnpm & Smmpm (#3921)

feat(pointer masking): support Ssnpm & Smnpm & Smmpm

fix(NC): fix a list of bugs of NC WMO access

* fix(PBMT): skip nc difftest and handle the conflict of nc and normal store

* fix(PBMT): nc st req is changed to a state machine execution

* fix(pbmt)

fix(NC): fix a list of bugs of NC WMO access

* fix(PBMT): skip nc difftest and handle the conflict of nc and normal store

* fix(PBMT): nc st req is changed to a state machine execution

* fix(pbmt): fix typo and control error of nc ld

* fix(pbmt): nc data assignment error

* fix(pbmt): nc should be used to wakeup

* fix(pbmt): remove wrong assert

* fix(pbmt): lots of bugs of nc st ld forward

* fix(pbmt): fix address align error

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feat(NCst): support WMO access of NC st

area(MemBlock): remove redundant signals to optimise area (#3560)

optimise redundant signals to reduce MemBlock area.
1. optimise 'exceptionVec', selected by LduCfg or StaCfg;
2. optimise 'fuType'

area(MemBlock): remove redundant signals to optimise area (#3560)

optimise redundant signals to reduce MemBlock area.
1. optimise 'exceptionVec', selected by LduCfg or StaCfg;
2. optimise 'fuType', reassign the value when writeback Rob in pipeline,
so no longer saved in LSQ.
3. optimise 'uop.imm', vaddr is computed in StoreMisalignBuffer and
there is no need to store the uop.imm.

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fix(misalign): enter storeMisalignBuffer when tlb hit (#3742)

In order to prevent some strange cases from occurring in store and
reduce complexity, let store enter storeMisalignBuffer only when tlb

fix(misalign): enter storeMisalignBuffer when tlb hit (#3742)

In order to prevent some strange cases from occurring in store and
reduce complexity, let store enter storeMisalignBuffer only when tlb
hits.

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