style(Bundles): rewrite bundles with new style (#4274)

style(Bundles): move bundles to Bundles.scala (#4247)

fix(L1PF, SMS): add pmp check (#4142)

**Checklist:**
1. no page/access fault
2. not uncache
3. no pmp access fault

**Changes:**
1. Add pmp response from PMPChecker
2. Wait until s3 phase to

fix(L1PF, SMS): add pmp check (#4142)

**Checklist:**
1. no page/access fault
2. not uncache
3. no pmp access fault

**Changes:**
1. Add pmp response from PMPChecker
2. Wait until s3 phase to process the response of TLB (got in s2) and
PMP(got in s3)

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feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 confi

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 configurations:

- PmemRanges: physical memory ranges
- PMAConfigs
- CHIAsyncBridge: set depth to 0 to disable it
- L2CacheConfig
- L3CacheConfig
- DebugModuleBaseAddr

For better human-readability, this commit changes `WithNKBL2/3` to
`L2/3CacheConfig`, changing to case classes, and making the first
parameter only accept human-readable size configuration like `0.5 MB` or
`256kB`.

This commit also changes PMAConfigs and PmemRanges into List of case
classes.

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fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condi

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condition is
not satisfied for prefetch and redirected requests, resulting in stuck.
This commit fixes this bug.

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fix(Pmem): memory range should be 'or'ed rather than 'and'ed (#3651)

refactor(Pmem): use `Seq` for physical memory ranges (#3622)

fix(prefetch): MMIO address should not send prefetch requests (#3615)

TODO: Prefetcher should check pmp & pma in order to decide whether to
send requests

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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LoadUnit: optimize generation of vaddr for tlb query

This commit remove `prefetch` from source vaddress, because it don't need to translate virtual address. We don't need to query tlb, but we need t

LoadUnit: optimize generation of vaddr for tlb query

This commit remove `prefetch` from source vaddress, because it don't need to translate virtual address. We don't need to query tlb, but we need to do pmp check, so we also need to send signal of `no_translate`.

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fanout: change entry reset into async-reset (#3229)

Prefetcher: use reg instead of wire when reordering for 3ld

prefetch & utility: add clockgate control (#3005)

fix bug of stream (#2756)

Bug Description：
(1) Increase the way of Dcache to 8 to reduce the problem of running on the bwaves test caused by too many addresses mapped to the same set.
(2) Set ldu0

fix bug of stream (#2756)

Bug Description：
(1) Increase the way of Dcache to 8 to reduce the problem of running on the bwaves test caused by too many addresses mapped to the same set.
(2) Set ldu0 to a high-confidence prefetch request channel to increase the probability that the prefetch request will be accepted by Dcache's MSHR.
(3) Fix the issue that ldu sends an error ready back to the prefetcher to prevent the prefetch request from being dropped.
(4) Dont let the prefetch request access Dcache's DataArray.
(5) Add a extra port in Muti-level prefetch Queue to accept more pf req from stream&stride
(6) Larger Stream bit vector Array 16 -> 32 to cover muti Stream access pattern in Bwaves and GemsFDTD.

In addition, the decline in libquantum is a bit strange.

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Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

RVH: support RISC-V Hypervisor Extension Version 1.0 (#2852)

This PR includes the implementation of RISC-V Hypervisor Extension Version 1.0.

Hypervisor extension mainly involves two-stage address

RVH: support RISC-V Hypervisor Extension Version 1.0 (#2852)

This PR includes the implementation of RISC-V Hypervisor Extension Version 1.0.

Hypervisor extension mainly involves two-stage address translation and some privileged CSR. Please refer to the RISC-V ISA manual privilege volume for details.

The main work is done by @pxk27.

Co-authored-by: peixiaokun <[email protected]>
Co-authored-by: Xu Zefan <[email protected]>
Co-authored-by: Haoyuan Feng <[email protected]>

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RVH: fix a problem about rtl code

L1Prefetch: fix x problem in l1 prefetch (#2862)

Since it is not controlled by the valid signal, source_1_older may become the x state, causing all prefetched training signals to become the x state.

Merge remote-tracking branch 'upstream/master' into tmp-backend-merge-fixtiming

chore: bump chisel 6.0.0 (#2654)

BREAKING CHANGE: `SimTop.v` / `XSTop.v` now generated in `build/rtl`

Merge remote-tracking branch 'upstream/master' into backendq

Rebase Timing Fix of Memblock from fix-timing branch (#2501)

* fix LQ timing

* l1pf: fix pf queue to ldu timing

* disable ecc path for timing analysis

* TODO: remove this

* fix pipeline

Rebase Timing Fix of Memblock from fix-timing branch (#2501)

* fix LQ timing

* l1pf: fix pf queue to ldu timing

* disable ecc path for timing analysis

* TODO: remove this

* fix pipeline

* memblock: add a Reg between inner/outer reset_vec

* missqueue: make mem_grant always ready

* Enable ECC path again

* remove fast replay reorder logic

* l1pf: use chosen of arbiter to improve timing

* remove reorder remain logic

* mq: use ParallelORR instead of orR

* Strengthen the conditions for load to load path for timing

* fix load to load data select for timing

* refactoring lq replay valid logic

* fix replay port

* fix load unit s0 arbitor logic

* add topdown wiring

* fix ldu ecc path

* remove lateKill

* ecc: physically remove ecc in DataArray

* loadpipe: use ParallelORR and ParallelMux for timing

* mainpipe: use ParallelMux and ParallelorR for timing

* fix fast replay is killed at s1

* fix replay cancel logic

* fix mq nack feedback logic

* sms: fix pf queue tlb req logic for timing

* kill load at s1

* fix loadqueuereplay enq logic

* opt raw rollback arbiter logic

* fix ecc_delayed writeback logic

* train all l1 pf and sms at load s3 for better timing

* disable load to load forward

* Revert "kill load at s1"

This reverts commit 56d47582ad4dd9c83373fb2db2a0709075485d4d.

* fix s0 kill logic

* ITLBRepeater: Add one more buffer when PTW resp

* remove trigger

* fix feedback_slow logic

* add latch in uncachebuffer rollback

* remove trigger in port

* fast replay: use dcache ready

* fix replay logic at s1

* uncache: fix uncache writeback

* fix delay kill logic

* fix clean exception loigc at s3

* fix ldu rollback logic

* fix ldu rollback valid logic

---------

Co-authored-by: sfencevma <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: good-circle <[email protected]>

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fix load/store enq io

fix merge error

Bump rocket-chip (#2353)