refactor(DFT): refactor `DFT` IO (#4530)

feat(dfx): integerate dfx components (#4312)

style(Bundles): rewrite bundles with new style (#4274)

style(Bundles): move bundles to Bundles.scala (#4247)

fix(L1PF, SMS): add pmp check (#4142)

**Checklist:**
1. no page/access fault
2. not uncache
3. no pmp access fault

**Changes:**
1. Add pmp response from PMPChecker
2. Wait until s3 phase to

fix(L1PF, SMS): add pmp check (#4142)

**Checklist:**
1. no page/access fault
2. not uncache
3. no pmp access fault

**Changes:**
1. Add pmp response from PMPChecker
2. Wait until s3 phase to process the response of TLB (got in s2) and
PMP(got in s3)

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feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 confi

feat(Config): add yaml parser for complicated parametrization (#4147)

This commit enables complicated parameterization by yaml parsing. We use
circe to do this.

In this commit, we implement 6 configurations:

- PmemRanges: physical memory ranges
- PMAConfigs
- CHIAsyncBridge: set depth to 0 to disable it
- L2CacheConfig
- L3CacheConfig
- DebugModuleBaseAddr

For better human-readability, this commit changes `WithNKBL2/3` to
`L2/3CacheConfig`, changing to case classes, and making the first
parameter only accept human-readable size configuration like `0.5 MB` or
`256kB`.

This commit also changes PMAConfigs and PmemRanges into List of case
classes.

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power(MemBlock): power optimization in MemBlock (#4059)

power optimization：
(1) use “withClockGate” instead of ClockGate in DCache
(2) reduce LSQ entries

docs: add acknowledgements (#3861)

power(MemBlock): add ClockGate for DCache SRAM (#3824)

By using ClockGate for DCache SRAM, memory Power has 64% reduction,
MemBlock total power has 23.38% reduction.

sms: update pht when act update (#3821)

when the bits update in act,it will be update in pht at the same time.

---------

Co-authored-by: jueshiwenli <[email protected]>

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condi

fix(TLB): Should not send gpa when prefetch or redirect (#3697)

In our previous design, it was assumed that a request for gpaddr would
always be replayed until it was responsed. However, this condition is
not satisfied for prefetch and redirected requests, resulting in stuck.
This commit fixes this bug.

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fix(Pmem): memory range should be 'or'ed rather than 'and'ed (#3651)

refactor(Pmem): use `Seq` for physical memory ranges (#3622)

fix(prefetch): MMIO address should not send prefetch requests (#3615)

TODO: Prefetcher should check pmp & pma in order to decide whether to
send requests

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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LoadUnit: optimize generation of vaddr for tlb query

This commit remove `prefetch` from source vaddress, because it don't need to translate virtual address. We don't need to query tlb, but we need t

LoadUnit: optimize generation of vaddr for tlb query

This commit remove `prefetch` from source vaddress, because it don't need to translate virtual address. We don't need to query tlb, but we need to do pmp check, so we also need to send signal of `no_translate`.

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prefetch & utility: add clockgate control (#3005)

Merge remote-tracking branch 'upstream/master' into tmp-master

TODO: add gpaddr data path from frontend to backend

RVH: fix bugs about hlvx in tlb and compile successfully

stIn: connect missing wire

MemBlock: enable 3ld3st (#2524)

* enable 3ld3st

* assign enqLsq

* fix IssQueSize

* remove performance regression

* MMU: Fix ptwrepeater when 3ld + 3st

* fix minimal config params

*

MemBlock: enable 3ld3st (#2524)

* enable 3ld3st

* assign enqLsq

* fix IssQueSize

* remove performance regression

* MMU: Fix ptwrepeater when 3ld + 3st

* fix minimal config params

* fix minimal config LoadQueueReplaySize

* add 3ld3st switch

* fix bank conflict valid logic

* fix strict memory ambiguous logic

* fix wakeup logic

* disable 3ld3st by default

* modify minimal config params

---------

Co-authored-by: Lyn <[email protected]>
Co-authored-by: good-circle <[email protected]>

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Merge remote-tracking branch 'upstream/master' into backendq

Rebase Timing Fix of Memblock from fix-timing branch (#2501)

* fix LQ timing

* l1pf: fix pf queue to ldu timing

* disable ecc path for timing analysis

* TODO: remove this

* fix pipeline

Rebase Timing Fix of Memblock from fix-timing branch (#2501)

* fix LQ timing

* l1pf: fix pf queue to ldu timing

* disable ecc path for timing analysis

* TODO: remove this

* fix pipeline

* memblock: add a Reg between inner/outer reset_vec

* missqueue: make mem_grant always ready

* Enable ECC path again

* remove fast replay reorder logic

* l1pf: use chosen of arbiter to improve timing

* remove reorder remain logic

* mq: use ParallelORR instead of orR

* Strengthen the conditions for load to load path for timing

* fix load to load data select for timing

* refactoring lq replay valid logic

* fix replay port

* fix load unit s0 arbitor logic

* add topdown wiring

* fix ldu ecc path

* remove lateKill

* ecc: physically remove ecc in DataArray

* loadpipe: use ParallelORR and ParallelMux for timing

* mainpipe: use ParallelMux and ParallelorR for timing

* fix fast replay is killed at s1

* fix replay cancel logic

* fix mq nack feedback logic

* sms: fix pf queue tlb req logic for timing

* kill load at s1

* fix loadqueuereplay enq logic

* opt raw rollback arbiter logic

* fix ecc_delayed writeback logic

* train all l1 pf and sms at load s3 for better timing

* disable load to load forward

* Revert "kill load at s1"

This reverts commit 56d47582ad4dd9c83373fb2db2a0709075485d4d.

* fix s0 kill logic

* ITLBRepeater: Add one more buffer when PTW resp

* remove trigger

* fix feedback_slow logic

* add latch in uncachebuffer rollback

* remove trigger in port

* fast replay: use dcache ready

* fix replay logic at s1

* uncache: fix uncache writeback

* fix delay kill logic

* fix clean exception loigc at s3

* fix ldu rollback logic

* fix ldu rollback valid logic

---------

Co-authored-by: sfencevma <[email protected]>
Co-authored-by: XiChen <[email protected]>
Co-authored-by: Lyn <[email protected]>
Co-authored-by: good-circle <[email protected]>

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fix params

sms: evict agt entry when dcache refill (#2437)

* sms: evict agt entry when dcache refill

* fix compile

* sms: evict on any region match