fix(VLSU): modifying vector misalign elemidx generation (#4593)

For "unit-stride access with element granularity misaligned and emul<0",
it could be the case that:
has only once valid elements, but

fix(VLSU): modifying vector misalign elemidx generation (#4593)

For "unit-stride access with element granularity misaligned and emul<0",
it could be the case that:
has only once valid elements, but splits into two flows(misaligned),
which would result in the `elemidx` being the same, making it impossible
for the exception handling logic in the `mergebuffer` to recognise the
correct order.

Instead of adding a new variable, we have chosen to reuse `elemidx` as a
marker. But this does pollute the original semantics of `elemidx`.

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fix(LSU): fix cbo instr exceptions and implementation (#4262)

1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly

fix(LSU): fix cbo instr exceptions and implementation (#4262)

1. typo.
2. `cbo` instr not produce misaligned exception.
3. `cbo zero` instr need flush `sbuffer`.
4. `cbo zero` sets mask correctly
5. Adding RAW checks to `cbo zero`.
6. Adding trigger(Debug Mode) checks to `cbo zero`.
7. Fixed several issues with the CBO instruction in NEMU.
----

In order not to create ambiguity with `io.mmioStout`, a new port of
`StoreQueue` is introduced for writeback `cbo zero` after flush sbuffer.
arbitration is performed in `MemBlock`, and currently, `cbo zero` has
higher priority by default.
`cbo zero` should not be writteback at the same time as `mmio`.

---
A check on `CacheLine` has been added to `RAWQueue` to ensure memory
consistency when executing `cbo zero`.
See this issues:https://github.com/OpenXiangShan/XiangShan/issues/4240
for specific issues.

---
The `cbo` instruction requires a trigger check.

---------

Co-authored-by: zhanglinjuan <[email protected]>

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fix(VLSU): fix vector exception writeback to 'MergeBuffer' logic (#4137)

Fixed the bug of abnormal signal loss when writing back.

Previously, we expected to compare only the ports of the writebacks

fix(VLSU): fix vector exception writeback to 'MergeBuffer' logic (#4137)

Fixed the bug of abnormal signal loss when writing back.

Previously, we expected to compare only the ports of the writebacks that
triggered the exception and pick the oldest.

But amazingly, I just realised that the implementation doesn't match the
annotation. The current implementation can be problematic in that if
the write-back port that did not have an exception is older, the port that
triggered the exception is not elected.

Use s3_exception to try to optimise timing.

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feat(NCst): support WMO access of NC st

refactor(MemBlock): turn on `dontTouch` only when debugging (#3792)

This will result in the delivery of clean generated code and may remove
some of the pseudo-paths.

fix(VLSU): new vstart calculation method is adopted

feat(rv64v): support first only fault instruction

feat(VLSU): element in which the exception occurs needs to retain its old value

feat(VLSU): set vstart when the support vector accesses anomalies

feat(Trigger): add vector memory access Trigger logic

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retain

fix(exception): fix exception vaddr generate logic (#3639)

In LSU, for exceptions that can be detected before address
translation(`preaf`, `prepf` or `pregpf`), the original vaddr should be
retained. And for exceptions detected after address translation, the
48-bit vaddr needs to be zero-extended or sign-extended according to
different modes(`GenExceptionVa`), and then write to *tval.

Also fix some connection bugs.

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feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault t

feat(trap): support m/htinst for specific G-stage translation (#3604)

According to RISC-V priv spec, mtinst/htinst could be always written
zero on trap into M/HS-mode, except for Guest-Page-Fault traps that meet
both of the following conditions:
- the trap is caused by a G-stage translation which supports VS-stage
translation
- a nonzero value is written to mtval2/htval

"isForVSnonLeafPTE" is used only in exceptional circumstances that gpf
happens in the G-stage translation which supports VS-stage translation,
such as searching the non-leaf pte of VS-stage.

This patch adds support for writing proper value to mtinst/htinst when
specific trap occurs. And bump the nemu.

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feat: implement a new version of reset tree (#3546)

This commit uses `LazyRawModuleImp` to implement L2Top, MemBlock,
Backend and frontend so that when `--reset-gen` option is enabled, reset
input

feat: implement a new version of reset tree (#3546)

This commit uses `LazyRawModuleImp` to implement L2Top, MemBlock,
Backend and frontend so that when `--reset-gen` option is enabled, reset
input of these modules will go through `ResetGen` and then drives the
reset of the registers inside the module.

<img
src="https://github.com/user-attachments/assets/1f544afe-4644-4604-ba6f-d14d31909f78"
width="50%">

---------
Co-authored-by: chengguanghui <[email protected]>

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fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exc

fix(exception): check high address bits of lsu (#3596)

In previous implementation, we simply truncated the higher bits of jump
target or load & store address, which made it impossible to raise
exceptions in such cases.

Commit
https://github.com/OpenXiangShan/XiangShan/commit/c1b28b66879239a5b3a44741376f3b002e8ac834
has already fixed high address bits checking of jump target. This commit
fixes lsu part, checking full address in tlb and passing full address
directly to csr.

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fix(VLSU): fix vector unit-stride address truncation (#3589)

fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix

fix(exception): Add guest page fault logic of misalign and vlsu (#3537)

In our previous design, we did not consider the handling of gpf of
unaligned & vector load and stores. This commit adds a fix to correctly
return the guest paddr when gpf happens in the above instructions.

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timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Opt

timing(MemBlock): optimize MemBlock timing (#3467)

This PR optimizes the timing of MemBlock. Specific optimizations include
but are not limited to:
+ TLB use the redirect for the next cycle
+ Optimize VLSU feedback and redirect
+ Optimise ldCancel and writeback signal generation
+ Optimise TLB Query Vaddr/hlv/hlvx/valid etc
+ Delay MMIO Store writeback for 1 Cycle
+ Fix tlbNoQuery and pmp logic
+ Remove clock gating for s3_fast_rep
+ Remove wbq conflict check to LoadPipe/MainPipe
+ Remove Mux in dcache resp data
+ Optimise data generation logic of LoadUnit
+ Duplicate Register in LoadUnit for data writeback
+ Duplicate Register in loadPipe for missQueue enq
+ Add skid buffer in VLSU
+ Select data from metaArray at S1
+ Simplify the enqueuing logic of missQueue
+ Separately generate the ready logic of miss Queue
+ Relax the conditions valid for bankdataArray reads
+ Add Reg between Dcache Mainpipe with sms prefetcher
+ Optimise store exceptionBuffer pipeline

---------

Co-authored-by: weiding liu <[email protected]>
Co-authored-by: Charlie Liu <[email protected]>
Co-authored-by: good-circle <[email protected]>

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Vsplit: optimize generate of ready for vector issue

VLSU: Modify the width of Veew when decode and remove some useless api (#3258)

VLSU: fix bugs related to vector access exceptions (#3169)

fix the bug of vector unit-stride exception address calculation

fix connection between vector exception and 'exceptionBuffer' in 'LoadQu

VLSU: fix bugs related to vector access exceptions (#3169)

fix the bug of vector unit-stride exception address calculation

fix connection between vector exception and 'exceptionBuffer' in 'LoadQueue'

At present, the vector access exception processing still needs to wait
for the modification of the back-end. We will test after the back-end is
completed, and may also adapt the storage access side.

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VSegmentUnit: fix SegmentIndex instruction splitPtr related computation logic.

Vsplit: Parameterised splitting address 128-bits alignment checking

VSegmentUnit: fix vdidxInField of writeback

VLSU: fix vector exception vaddr calculation

This commit fix the bug of vector exception vaddr calculation, need to send exceptionVec to exceptionBuffer.

VLSU: add suport of segment instruction

* segment Unit-Stride
* segment Stride
* segment order/unorder Index
TODO: except for order segment Index, other segment instruction can be executed out of or

VLSU: add suport of segment instruction

* segment Unit-Stride
* segment Stride
* segment order/unorder Index
TODO: except for order segment Index, other segment instruction can be executed out of order.

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