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db8c69b6 |
| 22-Feb-2024 |
robgar2001 <[email protected]> |
Fixed errors during compilation of OpenWRT kernel modules
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849c3b5e |
| 12-Sep-2023 |
Xianjun Jiao <[email protected]> |
Fix typo of printing in tx_intf.c
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75d924e0 |
| 17-Jan-2023 |
Xianjun Jiao <[email protected]> |
Remove unnecessary reg code in tx_intf.c
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d4c3d810 |
| 17-Jan-2023 |
Xianjun Jiao <[email protected]> |
Though the SIFS definition in 2.4GHz is 10us, the actual gap is still 16us: 1. Confirmed by CMW270 in OFDM mode (10us is for 11b where viterbi decoder is not needed) 2. See Signal Extension in 18.3.2
Though the SIFS definition in 2.4GHz is 10us, the actual gap is still 16us: 1. Confirmed by CMW270 in OFDM mode (10us is for 11b where viterbi decoder is not needed) 2. See Signal Extension in 18.3.2.4 ERP-OFDM PPDU format of 802.11-2020
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54c67c7a |
| 28-Mar-2022 |
Xianjun Jiao <[email protected]> |
No need to consider 4 last pkt from 4 queue in master branch: Always assume Linux schedule 4 priority queue to 4 FPGA queue via 1 on 1 mapping
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0cbb6873 |
| 28-Mar-2022 |
Xianjun Jiao <[email protected]> |
Change the default bb_gain from 290 to 250 in tx_intf:
- 2022-03-04 detailed test result: - - bb_gain 290 work for 11a/g all mcs - - bb_gain 290 work for 11n mcs 1~7 (aggr and non aggr) - - bb_gain
Change the default bb_gain from 290 to 250 in tx_intf:
- 2022-03-04 detailed test result: - - bb_gain 290 work for 11a/g all mcs - - bb_gain 290 work for 11n mcs 1~7 (aggr and non aggr) - - bb_gain 290 destroy 11n mcs 0 long (MTU 1500) tx pkt due to high PAPR (Peak to Average Power Ratio) - - bb_gain 250 work for 11n mcs 0 So, a conservative bb_gain 250 should be used
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469b96d3 |
| 28-Mar-2022 |
Xianjun Jiao <[email protected]> |
Remove/modify the tx_intf register API according to the new FPGA: 1. mixer/duc is not needed because we will not use offset tuning after the ad9361 tx lo control via FPGA is supported. 2. source sele
Remove/modify the tx_intf register API according to the new FPGA: 1. mixer/duc is not needed because we will not use offset tuning after the ad9361 tx lo control via FPGA is supported. 2. source selection register is not needed as well. 3. arbitrary IQ register is added.
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0c0d5d82 |
| 06-Jan-2022 |
mmehari <[email protected]> |
use FPGA fifo count registers instead of software queue_cnt
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2d12c07d |
| 06-Jan-2022 |
mmehari <[email protected]> |
tx_intf update: PKT_INFO*_[read/write] handlers and openwifi_fpga_type
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f738aefa |
| 06-Jan-2022 |
mmehari <[email protected]> |
A-MPDU tx aggregation support
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d14d06e5 |
| 13-May-2021 |
Xianjun Jiao <[email protected]> |
CSI fuzzer feature -- document to be finished
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95d3c7c5 |
| 05-Apr-2021 |
Xianjun Jiao <[email protected]> |
remove all the compiling warnings when build 32bit driver
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55c2866f |
| 03-Feb-2021 |
Jiao Xianjun <[email protected]> |
Merge pull request #54 from lnceballosz/master
NGI0 - Updating licensing aspects according REUSE
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c4306a8b |
| 03-Feb-2021 |
Jiao Xianjun <[email protected]> |
Update tx_intf.c
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a6085186 |
| 20-Jan-2021 |
Lina Ceballos <[email protected]> |
adding license and copyright headers
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6e3730c0 |
| 29-Dec-2020 |
mmehari <[email protected]> |
Linux queue waking/sleeping decision update: LARGE FPGA models were using small MAX_NUM_DMA_SYMBOL but now is based on /proc/device-tree/model information
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22dd0cc4 |
| 08-Oct-2020 |
Xianjun Jiao <[email protected]> |
the side channel (timestamp, frequency offset, CSI, equalizer) feature
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838a9007 |
| 12-Jun-2020 |
Xianjun Jiao <[email protected]> |
update source coed of: 4 fpga queues and better driver/fpga flow control to avoid crash. improved slice cfg and printing
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febc5adf |
| 27-Apr-2020 |
Xianjun Jiao <[email protected]> |
prepare upgrade
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b73660ad |
| 04-Mar-2020 |
Xianjun Jiao <[email protected]> |
prepare for release
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2ee67178 |
| 10-Dec-2019 |
Xianjun Jiao <[email protected]> |
initial commit
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