Lines Matching refs:debug_seqNum

80   val debug_seqNum = InstSeqNum()  constant
87   val debug_seqNum = InstSeqNum()  constant
108 …PerfCCT.updateInstPos(io.in.bits.debug_seqNum, PerfCCT.InstPos.AtFU.id.U, io.in.valid, clock, rese…
109 …PerfCCT.updateInstPos(io.out.bits.debug_seqNum, PerfCCT.InstPos.AtBypassVal.id.U, io.out.valid, cl…
126     io.out.bits.debug_seqNum := RegEnable(io.in.bits.debug_seqNum, io.in.fire)
142     io.out.bits.debug_seqNum := DataHoldBypass(io.in.bits.debug_seqNum, io.in.fire)
158     io.out.bits.debug_seqNum := io.in.bits.debug_seqNum
178 … val seqNumVec = init.debug_seqNum +: Seq.fill(latency)(Reg(chiselTypeOf(io.in.bits.debug_seqNum)))
199       case(((ctrl,data), perf), debug_seqNum) => {
207         out.debug_seqNum := debug_seqNum
217   val seqNumVec = pipeReg.map(_.debug_seqNum)
227   fixtiminginit.debug_seqNum := seqNumVec.last
233   val fixSeqNumVec = fixpipeReg.map(_.debug_seqNum)
249   io.out.bits.debug_seqNum := fixSeqNumVec.last