| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/ |
| H A D | X86CondBrFolding.cpp | 95 int CmpValue; member
141 int CmpValue = MBBInfo->CmpValue; in findPath() local
436 int &CmpValue) { in analyzeCompare()
486 int CmpValue; in analyzeMBB() local
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| H A D | X86InstrInfo.cpp | 3552 int CmpValue, in optimizeCompareInstr()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 285 int CmpValue, const MachineRegisterInfo *MRI) const { in optimizeCompareInstr()
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| /aosp_15_r20/external/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 287 int CmpValue, const MachineRegisterInfo *MRI) const { in optimizeCompareInstr()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 285 int64_t /*CmpMask*/, int64_t CmpValue, in optimizeCompareInstr() argument
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1459 int64_t CmpValue, const MachineRegisterInfo *MRI) const { in optimizeCompareInstr()
1750 int CmpValue, const TargetRegisterInfo &TRI, in canCmpInstrBeRemoved()
1844 MachineInstr &CmpInstr, unsigned SrcReg, int CmpValue, in removeCmpToZeroOrOne()
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| /aosp_15_r20/external/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 566 int CmpMask, CmpValue; in optimizeCmpInstr() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 628 int64_t CmpMask, CmpValue; in optimizeCmpInstr() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | PeepholeOptimizer.cpp | 611 int CmpMask, CmpValue; in optimizeCmpInstr() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 2883 int CmpValue, const MachineRegisterInfo *MRI) const { in optimizeCompareInstr()
3170 int CmpMask, CmpValue; in shouldSink() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 1455 int64_t CmpMask = 0, CmpValue = 0; in loopCountMayWrapOrUnderFlow() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 3029 int64_t CmpValue, const MachineRegisterInfo *MRI) const { in optimizeCompareInstr()
3316 int64_t CmpMask, CmpValue; in shouldSink() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 1459 int CmpMask = 0, CmpValue = 0; in loopCountMayWrapOrUnderFlow() local
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| /aosp_15_r20/external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonHardwareLoops.cpp | 1421 int CmpMask = 0, CmpValue = 0; in loopCountMayWrapOrUnderFlow() local
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| /aosp_15_r20/external/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 884 int CmpValue, const MachineRegisterInfo *MRI) const { in optimizeCompareInstr()
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| /aosp_15_r20/external/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.cpp | 2393 int CmpValue, const MachineRegisterInfo *MRI) const { in optimizeCompareInstr()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrInfo.cpp | 1184 int CmpValue, const MachineRegisterInfo *MRI) const { in optimizeCompareInstr()
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| /aosp_15_r20/external/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 5046 int CmpValue, in optimizeCompareInstr()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.cpp | 2777 int64_t CmpMask, CmpValue; in optimizeCmpPostRA() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/ |
| H A D | X86InstrInfo.cpp | 4313 int64_t CmpValue, in optimizeCompareInstr()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIInstrInfo.cpp | 8565 int64_t CmpValue, in optimizeCompareInstr()
|