/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
H A D | HexagonConstPropagation.cpp | 635 RegisterSubReg DefR(MD); in visitPHI() local 705 RegisterSubReg DefR(MO); in visitNonBranch() local 1937 RegisterSubReg DefR(MD); in evaluate() local 2586 RegisterSubReg DefR(MI.getOperand(0)); in evaluateHexCompare() local 2670 RegisterSubReg DefR(MI.getOperand(0)); in evaluateHexLogical() local 2694 RegisterSubReg DefR(MI.getOperand(0)); in evaluateHexCondMove() local 2752 RegisterSubReg DefR(MI.getOperand(0)); in evaluateHexExt() local 2766 RegisterSubReg DefR(MI.getOperand(0)); in evaluateHexVector1() local 2971 RegisterSubReg DefR(MI.getOperand(0)); in rewriteHexConstUses() local 3055 RegisterSubReg DefR(MI.getOperand(0)); in rewriteHexConstUses() local [all …]
|
H A D | HexagonEarlyIfConv.cpp | 441 Register DefR = MI.getOperand(0).getReg(); in isValid() local 993 Register DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
|
H A D | HexagonGenMux.cpp | 108 unsigned DefR, PredR; member
|
H A D | HexagonBitSimplify.cpp | 1221 Register DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local 2919 unsigned DefR; member 3162 unsigned DefR = Defs.find_first(); in processLoop() local
|
H A D | HexagonConstExtenders.cpp | 1529 llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in insertInitializer() local 1906 Register DefR = insertInitializer(Q.first, P.first); in replaceExtenders() local
|
H A D | HexagonOptAddrMode.cpp | 728 Register DefR = MI->getOperand(0).getReg(); in processBlock() local
|
H A D | HexagonBitTracker.cpp | 963 if (unsigned DefR = getUniqueDefVReg(MI)) { in evaluate() local
|
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
H A D | HexagonConstPropagation.cpp | 634 RegisterSubReg DefR(MD); in visitPHI() local 704 RegisterSubReg DefR(MO); in visitNonBranch() local 1936 RegisterSubReg DefR(MD); in evaluate() local 2585 RegisterSubReg DefR(MI.getOperand(0)); in evaluateHexCompare() local 2669 RegisterSubReg DefR(MI.getOperand(0)); in evaluateHexLogical() local 2693 RegisterSubReg DefR(MI.getOperand(0)); in evaluateHexCondMove() local 2751 RegisterSubReg DefR(MI.getOperand(0)); in evaluateHexExt() local 2765 RegisterSubReg DefR(MI.getOperand(0)); in evaluateHexVector1() local 2975 RegisterSubReg DefR(MI.getOperand(0)); in rewriteHexConstUses() local 3059 RegisterSubReg DefR(MI.getOperand(0)); in rewriteHexConstUses() local [all …]
|
H A D | HexagonEarlyIfConv.cpp | 441 Register DefR = MI.getOperand(0).getReg(); in isValid() local 993 Register DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
|
H A D | HexagonGenMux.cpp | 108 unsigned DefR, PredR; member
|
H A D | HexagonBitSimplify.cpp | 1250 Register DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local 2954 unsigned DefR; member 3196 Register DefR = Defs.find_first(); in processLoop() local
|
H A D | HexagonConstExtenders.cpp | 1530 llvm::Register DefR = MRI->createVirtualRegister(&Hexagon::IntRegsRegClass); in insertInitializer() local 1925 Register DefR = insertInitializer(Q.first, P.first); in replaceExtenders() local
|
H A D | HexagonOptAddrMode.cpp | 805 Register DefR = MI->getOperand(0).getReg(); in processBlock() local
|
H A D | HexagonBitTracker.cpp | 966 if (unsigned DefR = getUniqueDefVReg(MI)) { in evaluate() local
|
/aosp_15_r20/external/llvm/lib/Target/Hexagon/ |
H A D | HexagonEarlyIfConv.cpp | 418 unsigned DefR = MI.getOperand(0).getReg(); in isValid() local 957 unsigned DefR = PN->getOperand(0).getReg(); in eliminatePhis() local
|
H A D | RDFCopy.cpp | 59 RegisterRef DefR = { Dst.getReg(), Dst.getSubReg() }; in interpretAsCopy() local
|
H A D | HexagonBitSimplify.cpp | 1167 unsigned DefR = UseI.getOperand(0).getReg(); in computeUsedBits() local 2331 unsigned DefR; member 2581 unsigned DefR = Defs.find_first(); in processLoop() local
|
H A D | HexagonGenMux.cpp | 73 unsigned DefR, PredR; member
|
H A D | HexagonOptAddrMode.cpp | 530 unsigned DefR = MI->getOperand(0).getReg(); in processBlock() local
|