1package xiangshan.backend.datapath 2 3import chisel3.util.log2Up 4import org.chipsalliance.cde.config.Parameters 5import xiangshan.XSCoreParamsKey 6 7object DataConfig { 8 sealed abstract class DataConfig ( 9 val name: String, 10 val dataWidth: Int, 11 ) { 12 override def toString: String = name 13 } 14 15 case class IntData() extends DataConfig("int", 64) 16 case class FpData() extends DataConfig("fp", 64) 17 case class VecData() extends DataConfig("vec", 128) 18 case class ImmData(len: Int) extends DataConfig("int", len) 19 case class VAddrData()(implicit p: Parameters) extends DataConfig("vaddr", 48 + 2) // Todo: associate it with the width of vaddr 20 case class V0Data() extends DataConfig("v0", 128) 21 case class VlData() extends DataConfig("vl", log2Up(VecData().dataWidth) + 1 ) // 8 22 case class FakeIntData() extends DataConfig("fakeint", 64) 23 case class NoData() extends DataConfig("nodata", 0) 24 25 def RegSrcDataSet : Set[DataConfig] = Set(IntData(), FpData(), VecData(), V0Data(), VlData()) 26 def IntRegSrcDataSet: Set[DataConfig] = Set(IntData()) 27 def FpRegSrcDataSet : Set[DataConfig] = Set(FpData()) 28 def VecRegSrcDataSet : Set[DataConfig] = Set(VecData()) 29 def V0RegSrcDataSet : Set[DataConfig] = Set(V0Data()) 30 def VlRegSrcDataSet : Set[DataConfig] = Set(VlData()) 31 32 33 def RegDataMaxWidth : Int = RegSrcDataSet.map(_.dataWidth).max 34 35 def VAddrBits(implicit p: Parameters): Int = { 36 def coreParams = p(XSCoreParamsKey) 37 if (coreParams.HasHExtension) { 38 if (coreParams.EnableSv48) 39 coreParams.GPAddrBitsSv48x4 40 else 41 coreParams.GPAddrBitsSv39x4 42 } else { 43 if (coreParams.EnableSv48) 44 coreParams.VAddrBitsSv48 45 else 46 coreParams.VAddrBitsSv39 47 } 48 // VAddrBits is Virtual Memory addr bits 49 } 50} 51