| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitTracker.cpp | 92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
123 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
131 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
281 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
288 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
289 -> BT::RegisterCell { in evaluate()
298 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
333 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
349 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
356 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() local
[all …]
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitTracker.cpp | 92 const TargetRegisterClass &RC = *MRI.getRegClass(Reg); in mask() local
125 if (const TargetRegisterClass *RC = TRI.getMinimalPhysRegClass(Reg)) in getPhysRegBitWidth() local
133 const TargetRegisterClass &RC, unsigned Idx) const { in composeWithSubRegIndex() argument
283 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
290 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
291 -> BT::RegisterCell { in evaluate()
300 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
335 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
351 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
358 RegisterCell RC = RegisterCell::self(Reg[0].Reg, RW); in evaluate() local
[all …]
|
| /aosp_15_r20/external/llvm/lib/Target/Hexagon/ |
| H A D | HexagonBitTracker.cpp | 82 const TargetRegisterClass *RC = MRI.getRegClass(Reg); in mask() local
211 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW) in evaluate()
218 auto half = [this] (const BT::RegisterCell &RC, unsigned N) in evaluate()
219 -> BT::RegisterCell { in evaluate()
228 RegisterCell RC = eXTR(Rt, I*BW, I*BW+BW).cat(eXTR(Rs, I*BW, I*BW+BW)); in evaluate() local
263 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
279 RegisterCell RC = RegisterCell(RW).insert(PC, BT::BitMask(0, PW-1)); in evaluate() local
284 RegisterCell RC = RegisterCell::self(Reg[0].Reg, W0); in evaluate() local
300 RegisterCell RC = eADD(eSXT(CW, W1), rc(2)); in evaluate() local
309 RegisterCell RC = eADD(eIMM(im(1), W0), eASL(rc(2), im(3))); in evaluate() local
[all …]
|
| /aosp_15_r20/external/llvm/include/llvm/IR/ |
| H A D | IRBuilder.h | 781 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
795 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
803 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
817 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
825 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
839 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
847 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
859 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
871 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
878 if (Constant *RC = dyn_cast<Constant>(RHS)) variable
[all …]
|
| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 126 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
138 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
297 TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
303 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
309 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
314 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
322 bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const { in isTypeLegalForClass()
336 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
[all …]
|
| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 126 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
138 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
288 TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
294 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
300 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
305 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
313 bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const { in isTypeLegalForClass()
327 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
[all …]
|
| D | RegisterClassInfo.h | 78 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
111 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
131 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
139 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
|
| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 126 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
131 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
138 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
143 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
288 TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
294 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
300 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
305 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
313 bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const { in isTypeLegalForClass()
327 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
[all …]
|
| D | RegisterClassInfo.h | 78 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
111 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
131 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
139 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 118 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
123 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
130 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
135 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
271 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
277 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
283 unsigned getSpillAlignment(const TargetRegisterClass &RC) const { in getSpillAlignment()
288 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
297 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
301 vt_iterator legalclasstypes_end(const TargetRegisterClass &RC) const { in legalclasstypes_end()
[all …]
|
| H A D | RegisterClassInfo.h | 73 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
89 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
96 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
106 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
122 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
130 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.h | 186 static bool isSGPRClass(const TargetRegisterClass *RC) { in isSGPRClass()
198 static bool isVGPRClass(const TargetRegisterClass *RC) { in isVGPRClass()
203 static bool isAGPRClass(const TargetRegisterClass *RC) { in isAGPRClass()
208 bool isVectorSuperClass(const TargetRegisterClass *RC) const { in isVectorSuperClass()
213 bool isVSSuperClass(const TargetRegisterClass *RC) const { in isVSSuperClass()
218 static bool hasVGPRs(const TargetRegisterClass *RC) { in hasVGPRs()
223 static bool hasAGPRs(const TargetRegisterClass *RC) { in hasAGPRs()
228 static bool hasSGPRs(const TargetRegisterClass *RC) { in hasSGPRs()
233 static bool hasVectorRegisters(const TargetRegisterClass *RC) { in hasVectorRegisters()
289 bool isDivergentRegClass(const TargetRegisterClass *RC) const override { in isDivergentRegClass()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 124 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
129 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
136 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
141 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
279 unsigned getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
285 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
291 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
296 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
304 bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const { in isTypeLegalForClass()
318 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
[all …]
|
| H A D | RegisterClassInfo.h | 78 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
111 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
127 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
135 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
|
| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 124 bool hasSubClass(const TargetRegisterClass *RC) const { in hasSubClass()
129 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq()
136 bool hasSuperClass(const TargetRegisterClass *RC) const { in hasSuperClass()
141 bool hasSuperClassEq(const TargetRegisterClass *RC) const { in hasSuperClassEq()
286 TypeSize getRegSizeInBits(const TargetRegisterClass &RC) const { in getRegSizeInBits()
292 unsigned getSpillSize(const TargetRegisterClass &RC) const { in getSpillSize()
298 Align getSpillAlign(const TargetRegisterClass &RC) const { in getSpillAlign()
303 bool isTypeLegalForClass(const TargetRegisterClass &RC, MVT T) const { in isTypeLegalForClass()
311 bool isTypeLegalForClass(const TargetRegisterClass &RC, LLT T) const { in isTypeLegalForClass()
325 vt_iterator legalclasstypes_begin(const TargetRegisterClass &RC) const { in legalclasstypes_begin()
[all …]
|
| D | RegisterClassInfo.h | 78 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
94 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
101 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
111 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
127 uint8_t getMinCost(const TargetRegisterClass *RC) const { in getMinCost()
135 unsigned getLastCostChange(const TargetRegisterClass *RC) const { in getLastCostChange()
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 449 const TargetRegisterClass *RC, in PPCEmitLoad()
606 const TargetRegisterClass *RC = in SelectLoad() local
623 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
987 auto RC = MRI.getRegClass(SrcReg); in SelectFPTrunc() local
1051 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1130 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1174 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1225 auto RC = MRI.getRegClass(SrcReg); in SelectFPToI() local
1280 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1442 const TargetRegisterClass *RC = in processCallArgs() local
[all …]
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 455 const TargetRegisterClass *RC, in PPCEmitLoad()
612 const TargetRegisterClass *RC = in SelectLoad() local
629 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
990 auto RC = MRI.getRegClass(SrcReg); in SelectFPTrunc() local
1053 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1132 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1176 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1227 auto RC = MRI.getRegClass(SrcReg); in SelectFPToI() local
1281 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1443 const TargetRegisterClass *RC = in processCallArgs() local
[all …]
|
| /aosp_15_r20/external/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 463 const TargetRegisterClass *RC, in PPCEmitLoad()
609 const TargetRegisterClass *RC = in SelectLoad() local
625 const TargetRegisterClass *RC = MRI.getRegClass(SrcReg); in PPCEmitStore() local
988 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in PPCMoveToFPReg() local
1051 const TargetRegisterClass *RC = &PPC::F8RCRegClass; in SelectIToFP() local
1095 const TargetRegisterClass *RC = in PPCMoveToIntReg() local
1184 const TargetRegisterClass *RC = in SelectBinaryIntOp() local
1346 const TargetRegisterClass *RC = in processCallArgs() local
1358 const TargetRegisterClass *RC = in processCallArgs() local
1675 const TargetRegisterClass *RC = in SelectRet() local
[all …]
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyExplicitLocals.cpp | 83 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode()
100 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode()
117 static unsigned getLocalSetOpcode(const TargetRegisterClass *RC) { in getLocalSetOpcode()
134 static unsigned getLocalTeeOpcode(const TargetRegisterClass *RC) { in getLocalTeeOpcode()
151 static MVT typeForRegClass(const TargetRegisterClass *RC) { in typeForRegClass()
243 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
278 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
353 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyExplicitLocals.cpp | 88 static unsigned getDropOpcode(const TargetRegisterClass *RC) { in getDropOpcode()
107 static unsigned getLocalGetOpcode(const TargetRegisterClass *RC) { in getLocalGetOpcode()
126 static unsigned getLocalSetOpcode(const TargetRegisterClass *RC) { in getLocalSetOpcode()
145 static unsigned getLocalTeeOpcode(const TargetRegisterClass *RC) { in getLocalTeeOpcode()
164 static MVT typeForRegClass(const TargetRegisterClass *RC) { in typeForRegClass()
274 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
307 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
379 const TargetRegisterClass *RC = MRI.getRegClass(OldReg); in runOnMachineFunction() local
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
383 const TargetRegisterClass *RC = in expandExtractElementF64() local
421 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
719 const TargetRegisterClass *RC = in emitEpilogue() local
834 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
[all …]
|
| /aosp_15_r20/external/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 154 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
169 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
187 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
212 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
244 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
293 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
356 const TargetRegisterClass *RC = in expandExtractElementF64() local
395 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
695 const TargetRegisterClass *RC = in emitEpilogue() local
812 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
[all …]
|
| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Mips/ |
| H A D | MipsSEFrameLowering.cpp | 173 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandLoadCCond() local
188 const TargetRegisterClass *RC = RegInfo.intRegClass(4); in expandStoreCCond() local
206 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandLoadACC() local
231 const TargetRegisterClass *RC = RegInfo.intRegClass(RegSize); in expandStoreACC() local
264 const TargetRegisterClass *RC = RegInfo.intRegClass(VRegSize); in expandCopyACC() local
317 const TargetRegisterClass *RC = &Mips::GPR32RegClass; in expandBuildPairF64() local
383 const TargetRegisterClass *RC = in expandExtractElementF64() local
421 const TargetRegisterClass *RC = ABI.ArePtrs64bit() ? in emitPrologue() local
719 const TargetRegisterClass *RC = in emitEpilogue() local
834 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg); in spillCalleeSavedRegisters() local
[all …]
|
| /aosp_15_r20/external/llvm/include/llvm/CodeGen/ |
| H A D | RegisterClassInfo.h | 70 const RCInfo &get(const TargetRegisterClass *RC) const { in get()
86 unsigned getNumAllocatableRegs(const TargetRegisterClass *RC) const { in getNumAllocatableRegs()
93 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder()
103 bool isProperSubClass(const TargetRegisterClass *RC) const { in isProperSubClass()
119 unsigned getMinCost(const TargetRegisterClass *RC) { in getMinCost()
127 unsigned getLastCostChange(const TargetRegisterClass *RC) { in getLastCostChange()
|