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Searched defs:Rd (Results 1 – 25 of 48) sorted by relevance

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/aosp_15_r20/prebuilts/go/linux-x86/src/crypto/sha1/
Dsha1block_arm.s33 #define Rd R5 // SHA-1 accumulator macro
85 #define FUNC1(Ra, Rb, Rc, Rd, Re) \ argument
92 #define FUNC2(Ra, Rb, Rc, Rd, Re) \ argument
98 #define FUNC3(Ra, Rb, Rc, Rd, Re) \ argument
109 #define MIX(Ra, Rb, Rc, Rd, Re) \ argument
115 #define ROUND1(Ra, Rb, Rc, Rd, Re) \ argument
120 #define ROUND1x(Ra, Rb, Rc, Rd, Re) \ argument
125 #define ROUND2(Ra, Rb, Rc, Rd, Re) \ argument
130 #define ROUND3(Ra, Rb, Rc, Rd, Re) \ argument
135 #define ROUND4(Ra, Rb, Rc, Rd, Re) \ argument
/aosp_15_r20/prebuilts/go/linux-x86/src/crypto/md5/
Dmd5block_arm.s17 #define Rd R5 // MD5 accumulator macro
71 #define ROUND1(Ra, Rb, Rc, Rd, index, shift, Rconst) \ argument
107 #define ROUND2(Ra, Rb, Rc, Rd, index, shift, Rconst) \ argument
143 #define ROUND3(Ra, Rb, Rc, Rd, index, shift, Rconst) \ argument
178 #define ROUND4(Ra, Rb, Rc, Rd, index, shift, Rconst) \ argument
/aosp_15_r20/external/capstone/arch/ARM/
H A DARMDisassembler.c1898 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeQADDInstruction() local
2103 unsigned Rd = fieldFromInstruction_4(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2127 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2154 unsigned Rd = fieldFromInstruction_4(Insn, 16, 4); in DecodeSMLAInstruction() local
2296 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLDInstruction() local
2630 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVSTInstruction() local
2902 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLD1DupInstruction() local
2950 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLD2DupInstruction() local
2999 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3035 unsigned Rd = fieldFromInstruction_4(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
/aosp_15_r20/external/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp652 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
743 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
805 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1296 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1353 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1384 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1423 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1440 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1459 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeBaseAddSubImm() local
/aosp_15_r20/external/capstone/arch/AArch64/
H A DAArch64Disassembler.c730 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
835 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
899 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1390 unsigned Rd, Rn, Rm; in DecodeAddSubERegInstruction() local
1450 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1483 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1523 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1541 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1559 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeBaseAddSubImm() local
/aosp_15_r20/external/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp1844 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2070 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2094 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2121 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2334 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLDInstruction() local
2659 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVSTInstruction() local
2930 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD1DupInstruction() local
2977 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD2DupInstruction() local
3025 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3060 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
/aosp_15_r20/external/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp159 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint()
243 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint()
363 unsigned Rd = MI.getOperand(0).getReg(); in apply() local
373 unsigned Rd = MI.getOperand(0).getReg(); in apply() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp158 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint()
242 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint()
362 Register Rd = MI.getOperand(0).getReg(); in apply() local
372 Register Rd = MI.getOperand(0).getReg(); in apply() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/
H A DAArch64PBQPRegAlloc.cpp158 bool A57ChainingConstraint::addIntraChainConstraint(PBQPRAGraph &G, unsigned Rd, in addIntraChainConstraint()
242 void A57ChainingConstraint::addInterChainConstraint(PBQPRAGraph &G, unsigned Rd, in addInterChainConstraint()
362 Register Rd = MI.getOperand(0).getReg(); in apply() local
372 Register Rd = MI.getOperand(0).getReg(); in apply() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp911 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
1010 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
1072 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1612 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1669 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1700 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1739 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1757 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1775 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubImmShift() local
2006 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeCPYMemOpInstruction() local
[all …]
/aosp_15_r20/external/rust/android-crates-io/crates/tokio/tests/
Dio_read_buf.rs13 struct Rd { in read_buf() struct
14 cnt: usize, in read_buf()
17 impl AsyncRead for Rd { in read_buf() implementation
Dio_read.rs19 struct Rd { in read() struct
20 poll_cnt: usize, in read()
23 impl AsyncRead for Rd { in read() implementation
Dio_copy.rs13 struct Rd(bool); in copy() struct
15 impl AsyncRead for Rd { in copy() implementation
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AArch64/Disassembler/
H A DAArch64Disassembler.cpp845 unsigned Rd = fieldFromInstruction(Insn, 0, 5); in DecodeFMOVLaneInstruction() local
936 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeThreeAddrSRegInstruction() local
998 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeMoveImmInstruction() local
1507 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubERegInstruction() local
1564 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeLogicalImmInstruction() local
1595 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmInstruction() local
1634 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeModImmTiedInstruction() local
1651 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAdrInstruction() local
1670 unsigned Rd = fieldFromInstruction(insn, 0, 5); in DecodeAddSubImmShift() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2429 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2685 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2710 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2738 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2962 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLDInstruction() local
3294 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVSTInstruction() local
3565 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD1DupInstruction() local
3613 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD2DupInstruction() local
3662 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3698 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/ARM/Disassembler/
H A DARMDisassembler.cpp2196 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeQADDInstruction() local
2422 unsigned Rd = fieldFromInstruction(Insn, 8, 4); in DecodeT2MOVTWInstruction() local
2446 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeArmMOVTWInstruction() local
2473 unsigned Rd = fieldFromInstruction(Insn, 16, 4); in DecodeSMLAInstruction() local
2685 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLDInstruction() local
3012 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVSTInstruction() local
3282 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD1DupInstruction() local
3329 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD2DupInstruction() local
3377 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD3DupInstruction() local
3412 unsigned Rd = fieldFromInstruction(Insn, 12, 4); in DecodeVLD4DupInstruction() local
[all …]
/aosp_15_r20/external/swiftshader/third_party/subzero/src/
H A DIceAssemblerMIPS32.cpp271 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName); in emitRdRtSa() local
284 const IValueT Rd = encodeGPRegister(OpRd, "Rd", InsnName); in emitRdRsRt() local
527 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "clz"); in clz() local
657 const IValueT Rd = in jalr() local
774 IValueT Rd = encodeGPRegister(OpRd, "Rd", "mfhi"); in mfhi() local
781 IValueT Rd = encodeGPRegister(OpRd, "Rd", "mflo"); in mflo() local
821 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "pseudo-move"); in move() local
840 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movf"); in movf() local
875 const IValueT Rd = encodeGPRegister(OpRd, "Rd", "movt"); in movt() local
H A DIceAssemblerARM32.cpp797 IValueT Rd, IValueT Imm12, in emitType01()
819 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitType01() local
825 IValueT Rd, IValueT Rn, const Operand *OpSrc1, in emitType01()
929 constexpr IValueT Rd = RegARM32::Encoded_Reg_r0; in emitCompareOp() local
1061 void AssemblerARM32::emitDivOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, in emitDivOp()
1128 void AssemblerARM32::emitMulOp(CondARM32::Cond Cond, IValueT Opcode, IValueT Rd, in emitMulOp()
1158 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitSignExtend() local
1464 IValueT Rd = encodeGPRegister(OpRd, RdName, ClzName); in clz() local
1624 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitMemExOp() local
1692 IValueT Rd = encodeGPRegister(OpRd, "Rd", InstName); in emitShift() local
[all …]
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp296 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs2() local
306 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1Rs2() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/RISCV/Disassembler/
H A DRISCVDisassembler.cpp413 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs2() local
423 unsigned Rd = fieldFromInstruction(Insn, 7, 5); in decodeRVCInstrRdRs1Rs2() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1680 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1713 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1723 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1911 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1691 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1724 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1734 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1922 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
/aosp_15_r20/external/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1903 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1942 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
1952 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
2150 MCOperand &Rd = Inst.getOperand(0); in processInstruction() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/LoongArch/AsmParser/
H A DLoongArchAsmParser.cpp1178 unsigned Rd = Inst.getOperand(0).getReg(); in checkTargetMatchPredicate() local
1190 unsigned Rd = Inst.getOperand(0).getReg(); in checkTargetMatchPredicate() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/MSP430/Disassembler/
H A DMSP430Disassembler.cpp194 unsigned Rd = fieldFromInstruction(Insn, 0, 4); in DecodeDstAddrMode() local

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