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Searched defs:SRL (Results 1 – 25 of 41) sorted by relevance

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/aosp_15_r20/external/libffi/src/mips/
H A Dffitarget.h152 # define SRL srl macro
159 # define SRL dsrl macro
/aosp_15_r20/external/python/cpython2/Modules/_ctypes/libffi/src/mips/
Dffitarget.h152 # define SRL srl macro
159 # define SRL dsrl macro
/aosp_15_r20/external/llvm/lib/Target/MSP430/
H A DMSP430ISelLowering.h65 SHL, SRA, SRL enumerator
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h36 SRL = 0x27, enumerator
/aosp_15_r20/external/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h37 SRL = 0x27, enumerator
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Lanai/
H A DLanaiAluCode.h36 SRL = 0x27, enumerator
/aosp_15_r20/external/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h106 SRL, SRA, SHL, enumerator
/aosp_15_r20/external/llvm/lib/Target/SystemZ/
H A DSystemZSelectionDAGInfo.cpp176 SDValue SRL = DAG.getNode(ISD::SRL, DL, MVT::i32, IPM, in addIPMSequence() local
H A DSystemZInstrInfo.cpp486 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI); in removeIPMBasedCompare() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h156 SRL, enumerator
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.h167 SRL, enumerator
/aosp_15_r20/external/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h339 SHL, SRA, SRL, ROTL, ROTR, enumerator
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h471 SHL, SRA, SRL, ROTL, ROTR, FSHL, FSHR, enumerator
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGen/
DISDOpcodes.h707 SRL, enumerator
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGen/
DISDOpcodes.h708 SRL, enumerator
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/CodeGen/
DISDOpcodes.h707 SRL, enumerator
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGen/
DISDOpcodes.h707 SRL, enumerator
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/
H A DISDOpcodes.h693 SRL, enumerator
/aosp_15_r20/external/llvm/include/llvm/TableGen/
H A DRecord.h801 enum BinaryOp : uint8_t { ADD, AND, SHL, SRA, SRL, LISTCONCAT, enumerator
/aosp_15_r20/external/pcre/src/sljit/
H A DsljitNativeRISCV_common.c133 #define SRL (F7(0x0) | F3(0x5) | OPC(0x33)) macro
H A DsljitNativeMIPS_common.c301 #define SRL (HI(0) | LO(2)) macro
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/include/llvm/TableGen/
H A DRecord.h803 enum BinaryOp : uint8_t { ADD, MUL, AND, OR, SHL, SRA, SRL, LISTCONCAT, enumerator
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/TableGen/
DRecord.h909 SRL, enumerator
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/TableGen/
DRecord.h909 SRL, enumerator
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/TableGen/
DRecord.h909 SRL, enumerator

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