1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
2 //
3 // The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13
14 #include "SystemZInstrInfo.h"
15 #include "SystemZInstrBuilder.h"
16 #include "SystemZTargetMachine.h"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/LiveIntervalAnalysis.h"
19 #include "llvm/CodeGen/MachineRegisterInfo.h"
20
21 using namespace llvm;
22
23 #define GET_INSTRINFO_CTOR_DTOR
24 #define GET_INSTRMAP_INFO
25 #include "SystemZGenInstrInfo.inc"
26
27 // Return a mask with Count low bits set.
allOnes(unsigned int Count)28 static uint64_t allOnes(unsigned int Count) {
29 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
30 }
31
32 // Reg should be a 32-bit GPR. Return true if it is a high register rather
33 // than a low register.
isHighReg(unsigned int Reg)34 static bool isHighReg(unsigned int Reg) {
35 if (SystemZ::GRH32BitRegClass.contains(Reg))
36 return true;
37 assert(SystemZ::GR32BitRegClass.contains(Reg) && "Invalid GRX32");
38 return false;
39 }
40
41 // Pin the vtable to this file.
anchor()42 void SystemZInstrInfo::anchor() {}
43
SystemZInstrInfo(SystemZSubtarget & sti)44 SystemZInstrInfo::SystemZInstrInfo(SystemZSubtarget &sti)
45 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
46 RI(), STI(sti) {
47 }
48
49 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
50 // each having the opcode given by NewOpcode.
splitMove(MachineBasicBlock::iterator MI,unsigned NewOpcode) const51 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
52 unsigned NewOpcode) const {
53 MachineBasicBlock *MBB = MI->getParent();
54 MachineFunction &MF = *MBB->getParent();
55
56 // Get two load or store instructions. Use the original instruction for one
57 // of them (arbitrarily the second here) and create a clone for the other.
58 MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
59 MBB->insert(MI, EarlierMI);
60
61 // Set up the two 64-bit registers.
62 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
63 MachineOperand &LowRegOp = MI->getOperand(0);
64 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
65 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
66
67 // The address in the first (high) instruction is already correct.
68 // Adjust the offset in the second (low) instruction.
69 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
70 MachineOperand &LowOffsetOp = MI->getOperand(2);
71 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
72
73 // Clear the kill flags for the base and index registers in the first
74 // instruction.
75 EarlierMI->getOperand(1).setIsKill(false);
76 EarlierMI->getOperand(3).setIsKill(false);
77
78 // Set the opcodes.
79 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
80 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
81 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
82
83 EarlierMI->setDesc(get(HighOpcode));
84 MI->setDesc(get(LowOpcode));
85 }
86
87 // Split ADJDYNALLOC instruction MI.
splitAdjDynAlloc(MachineBasicBlock::iterator MI) const88 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
89 MachineBasicBlock *MBB = MI->getParent();
90 MachineFunction &MF = *MBB->getParent();
91 MachineFrameInfo *MFFrame = MF.getFrameInfo();
92 MachineOperand &OffsetMO = MI->getOperand(2);
93
94 uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
95 SystemZMC::CallFrameSize +
96 OffsetMO.getImm());
97 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
98 assert(NewOpcode && "No support for huge argument lists yet");
99 MI->setDesc(get(NewOpcode));
100 OffsetMO.setImm(Offset);
101 }
102
103 // MI is an RI-style pseudo instruction. Replace it with LowOpcode
104 // if the first operand is a low GR32 and HighOpcode if the first operand
105 // is a high GR32. ConvertHigh is true if LowOpcode takes a signed operand
106 // and HighOpcode takes an unsigned 32-bit operand. In those cases,
107 // MI has the same kind of operand as LowOpcode, so needs to be converted
108 // if HighOpcode is used.
expandRIPseudo(MachineInstr & MI,unsigned LowOpcode,unsigned HighOpcode,bool ConvertHigh) const109 void SystemZInstrInfo::expandRIPseudo(MachineInstr &MI, unsigned LowOpcode,
110 unsigned HighOpcode,
111 bool ConvertHigh) const {
112 unsigned Reg = MI.getOperand(0).getReg();
113 bool IsHigh = isHighReg(Reg);
114 MI.setDesc(get(IsHigh ? HighOpcode : LowOpcode));
115 if (IsHigh && ConvertHigh)
116 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm()));
117 }
118
119 // MI is a three-operand RIE-style pseudo instruction. Replace it with
120 // LowOpcodeK if the registers are both low GR32s, otherwise use a move
121 // followed by HighOpcode or LowOpcode, depending on whether the target
122 // is a high or low GR32.
expandRIEPseudo(MachineInstr & MI,unsigned LowOpcode,unsigned LowOpcodeK,unsigned HighOpcode) const123 void SystemZInstrInfo::expandRIEPseudo(MachineInstr &MI, unsigned LowOpcode,
124 unsigned LowOpcodeK,
125 unsigned HighOpcode) const {
126 unsigned DestReg = MI.getOperand(0).getReg();
127 unsigned SrcReg = MI.getOperand(1).getReg();
128 bool DestIsHigh = isHighReg(DestReg);
129 bool SrcIsHigh = isHighReg(SrcReg);
130 if (!DestIsHigh && !SrcIsHigh)
131 MI.setDesc(get(LowOpcodeK));
132 else {
133 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(), DestReg, SrcReg,
134 SystemZ::LR, 32, MI.getOperand(1).isKill());
135 MI.setDesc(get(DestIsHigh ? HighOpcode : LowOpcode));
136 MI.getOperand(1).setReg(DestReg);
137 MI.tieOperands(0, 1);
138 }
139 }
140
141 // MI is an RXY-style pseudo instruction. Replace it with LowOpcode
142 // if the first operand is a low GR32 and HighOpcode if the first operand
143 // is a high GR32.
expandRXYPseudo(MachineInstr & MI,unsigned LowOpcode,unsigned HighOpcode) const144 void SystemZInstrInfo::expandRXYPseudo(MachineInstr &MI, unsigned LowOpcode,
145 unsigned HighOpcode) const {
146 unsigned Reg = MI.getOperand(0).getReg();
147 unsigned Opcode = getOpcodeForOffset(isHighReg(Reg) ? HighOpcode : LowOpcode,
148 MI.getOperand(2).getImm());
149 MI.setDesc(get(Opcode));
150 }
151
152 // MI is an RR-style pseudo instruction that zero-extends the low Size bits
153 // of one GRX32 into another. Replace it with LowOpcode if both operands
154 // are low registers, otherwise use RISB[LH]G.
expandZExtPseudo(MachineInstr & MI,unsigned LowOpcode,unsigned Size) const155 void SystemZInstrInfo::expandZExtPseudo(MachineInstr &MI, unsigned LowOpcode,
156 unsigned Size) const {
157 emitGRX32Move(*MI.getParent(), MI, MI.getDebugLoc(),
158 MI.getOperand(0).getReg(), MI.getOperand(1).getReg(), LowOpcode,
159 Size, MI.getOperand(1).isKill());
160 MI.eraseFromParent();
161 }
162
expandLoadStackGuard(MachineInstr * MI) const163 void SystemZInstrInfo::expandLoadStackGuard(MachineInstr *MI) const {
164 MachineBasicBlock *MBB = MI->getParent();
165 MachineFunction &MF = *MBB->getParent();
166 const unsigned Reg = MI->getOperand(0).getReg();
167
168 // Conveniently, all 4 instructions are cloned from LOAD_STACK_GUARD,
169 // so they already have operand 0 set to reg.
170
171 // ear <reg>, %a0
172 MachineInstr *Ear1MI = MF.CloneMachineInstr(MI);
173 MBB->insert(MI, Ear1MI);
174 Ear1MI->setDesc(get(SystemZ::EAR));
175 MachineInstrBuilder(MF, Ear1MI).addImm(0);
176
177 // sllg <reg>, <reg>, 32
178 MachineInstr *SllgMI = MF.CloneMachineInstr(MI);
179 MBB->insert(MI, SllgMI);
180 SllgMI->setDesc(get(SystemZ::SLLG));
181 MachineInstrBuilder(MF, SllgMI).addReg(Reg).addReg(0).addImm(32);
182
183 // ear <reg>, %a1
184 MachineInstr *Ear2MI = MF.CloneMachineInstr(MI);
185 MBB->insert(MI, Ear2MI);
186 Ear2MI->setDesc(get(SystemZ::EAR));
187 MachineInstrBuilder(MF, Ear2MI).addImm(1);
188
189 // lg <reg>, 40(<reg>)
190 MI->setDesc(get(SystemZ::LG));
191 MachineInstrBuilder(MF, MI).addReg(Reg).addImm(40).addReg(0);
192 }
193
194 // Emit a zero-extending move from 32-bit GPR SrcReg to 32-bit GPR
195 // DestReg before MBBI in MBB. Use LowLowOpcode when both DestReg and SrcReg
196 // are low registers, otherwise use RISB[LH]G. Size is the number of bits
197 // taken from the low end of SrcReg (8 for LLCR, 16 for LLHR and 32 for LR).
198 // KillSrc is true if this move is the last use of SrcReg.
emitGRX32Move(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const DebugLoc & DL,unsigned DestReg,unsigned SrcReg,unsigned LowLowOpcode,unsigned Size,bool KillSrc) const199 void SystemZInstrInfo::emitGRX32Move(MachineBasicBlock &MBB,
200 MachineBasicBlock::iterator MBBI,
201 const DebugLoc &DL, unsigned DestReg,
202 unsigned SrcReg, unsigned LowLowOpcode,
203 unsigned Size, bool KillSrc) const {
204 unsigned Opcode;
205 bool DestIsHigh = isHighReg(DestReg);
206 bool SrcIsHigh = isHighReg(SrcReg);
207 if (DestIsHigh && SrcIsHigh)
208 Opcode = SystemZ::RISBHH;
209 else if (DestIsHigh && !SrcIsHigh)
210 Opcode = SystemZ::RISBHL;
211 else if (!DestIsHigh && SrcIsHigh)
212 Opcode = SystemZ::RISBLH;
213 else {
214 BuildMI(MBB, MBBI, DL, get(LowLowOpcode), DestReg)
215 .addReg(SrcReg, getKillRegState(KillSrc));
216 return;
217 }
218 unsigned Rotate = (DestIsHigh != SrcIsHigh ? 32 : 0);
219 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
220 .addReg(DestReg, RegState::Undef)
221 .addReg(SrcReg, getKillRegState(KillSrc))
222 .addImm(32 - Size).addImm(128 + 31).addImm(Rotate);
223 }
224
225 // If MI is a simple load or store for a frame object, return the register
226 // it loads or stores and set FrameIndex to the index of the frame object.
227 // Return 0 otherwise.
228 //
229 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
isSimpleMove(const MachineInstr & MI,int & FrameIndex,unsigned Flag)230 static int isSimpleMove(const MachineInstr &MI, int &FrameIndex,
231 unsigned Flag) {
232 const MCInstrDesc &MCID = MI.getDesc();
233 if ((MCID.TSFlags & Flag) && MI.getOperand(1).isFI() &&
234 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) {
235 FrameIndex = MI.getOperand(1).getIndex();
236 return MI.getOperand(0).getReg();
237 }
238 return 0;
239 }
240
isLoadFromStackSlot(const MachineInstr & MI,int & FrameIndex) const241 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
242 int &FrameIndex) const {
243 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
244 }
245
isStoreToStackSlot(const MachineInstr & MI,int & FrameIndex) const246 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
247 int &FrameIndex) const {
248 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
249 }
250
isStackSlotCopy(const MachineInstr & MI,int & DestFrameIndex,int & SrcFrameIndex) const251 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr &MI,
252 int &DestFrameIndex,
253 int &SrcFrameIndex) const {
254 // Check for MVC 0(Length,FI1),0(FI2)
255 const MachineFrameInfo *MFI = MI.getParent()->getParent()->getFrameInfo();
256 if (MI.getOpcode() != SystemZ::MVC || !MI.getOperand(0).isFI() ||
257 MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() ||
258 MI.getOperand(4).getImm() != 0)
259 return false;
260
261 // Check that Length covers the full slots.
262 int64_t Length = MI.getOperand(2).getImm();
263 unsigned FI1 = MI.getOperand(0).getIndex();
264 unsigned FI2 = MI.getOperand(3).getIndex();
265 if (MFI->getObjectSize(FI1) != Length ||
266 MFI->getObjectSize(FI2) != Length)
267 return false;
268
269 DestFrameIndex = FI1;
270 SrcFrameIndex = FI2;
271 return true;
272 }
273
analyzeBranch(MachineBasicBlock & MBB,MachineBasicBlock * & TBB,MachineBasicBlock * & FBB,SmallVectorImpl<MachineOperand> & Cond,bool AllowModify) const274 bool SystemZInstrInfo::analyzeBranch(MachineBasicBlock &MBB,
275 MachineBasicBlock *&TBB,
276 MachineBasicBlock *&FBB,
277 SmallVectorImpl<MachineOperand> &Cond,
278 bool AllowModify) const {
279 // Most of the code and comments here are boilerplate.
280
281 // Start from the bottom of the block and work up, examining the
282 // terminator instructions.
283 MachineBasicBlock::iterator I = MBB.end();
284 while (I != MBB.begin()) {
285 --I;
286 if (I->isDebugValue())
287 continue;
288
289 // Working from the bottom, when we see a non-terminator instruction, we're
290 // done.
291 if (!isUnpredicatedTerminator(*I))
292 break;
293
294 // A terminator that isn't a branch can't easily be handled by this
295 // analysis.
296 if (!I->isBranch())
297 return true;
298
299 // Can't handle indirect branches.
300 SystemZII::Branch Branch(getBranchInfo(*I));
301 if (!Branch.Target->isMBB())
302 return true;
303
304 // Punt on compound branches.
305 if (Branch.Type != SystemZII::BranchNormal)
306 return true;
307
308 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
309 // Handle unconditional branches.
310 if (!AllowModify) {
311 TBB = Branch.Target->getMBB();
312 continue;
313 }
314
315 // If the block has any instructions after a JMP, delete them.
316 while (std::next(I) != MBB.end())
317 std::next(I)->eraseFromParent();
318
319 Cond.clear();
320 FBB = nullptr;
321
322 // Delete the JMP if it's equivalent to a fall-through.
323 if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
324 TBB = nullptr;
325 I->eraseFromParent();
326 I = MBB.end();
327 continue;
328 }
329
330 // TBB is used to indicate the unconditinal destination.
331 TBB = Branch.Target->getMBB();
332 continue;
333 }
334
335 // Working from the bottom, handle the first conditional branch.
336 if (Cond.empty()) {
337 // FIXME: add X86-style branch swap
338 FBB = TBB;
339 TBB = Branch.Target->getMBB();
340 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
341 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
342 continue;
343 }
344
345 // Handle subsequent conditional branches.
346 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
347
348 // Only handle the case where all conditional branches branch to the same
349 // destination.
350 if (TBB != Branch.Target->getMBB())
351 return true;
352
353 // If the conditions are the same, we can leave them alone.
354 unsigned OldCCValid = Cond[0].getImm();
355 unsigned OldCCMask = Cond[1].getImm();
356 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
357 continue;
358
359 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
360 return false;
361 }
362
363 return false;
364 }
365
RemoveBranch(MachineBasicBlock & MBB) const366 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
367 // Most of the code and comments here are boilerplate.
368 MachineBasicBlock::iterator I = MBB.end();
369 unsigned Count = 0;
370
371 while (I != MBB.begin()) {
372 --I;
373 if (I->isDebugValue())
374 continue;
375 if (!I->isBranch())
376 break;
377 if (!getBranchInfo(*I).Target->isMBB())
378 break;
379 // Remove the branch.
380 I->eraseFromParent();
381 I = MBB.end();
382 ++Count;
383 }
384
385 return Count;
386 }
387
388 bool SystemZInstrInfo::
ReverseBranchCondition(SmallVectorImpl<MachineOperand> & Cond) const389 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
390 assert(Cond.size() == 2 && "Invalid condition");
391 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
392 return false;
393 }
394
InsertBranch(MachineBasicBlock & MBB,MachineBasicBlock * TBB,MachineBasicBlock * FBB,ArrayRef<MachineOperand> Cond,const DebugLoc & DL) const395 unsigned SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB,
396 MachineBasicBlock *TBB,
397 MachineBasicBlock *FBB,
398 ArrayRef<MachineOperand> Cond,
399 const DebugLoc &DL) const {
400 // In this function we output 32-bit branches, which should always
401 // have enough range. They can be shortened and relaxed by later code
402 // in the pipeline, if desired.
403
404 // Shouldn't be a fall through.
405 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
406 assert((Cond.size() == 2 || Cond.size() == 0) &&
407 "SystemZ branch conditions have one component!");
408
409 if (Cond.empty()) {
410 // Unconditional branch?
411 assert(!FBB && "Unconditional branch with multiple successors!");
412 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
413 return 1;
414 }
415
416 // Conditional branch.
417 unsigned Count = 0;
418 unsigned CCValid = Cond[0].getImm();
419 unsigned CCMask = Cond[1].getImm();
420 BuildMI(&MBB, DL, get(SystemZ::BRC))
421 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
422 ++Count;
423
424 if (FBB) {
425 // Two-way Conditional branch. Insert the second branch.
426 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
427 ++Count;
428 }
429 return Count;
430 }
431
analyzeCompare(const MachineInstr & MI,unsigned & SrcReg,unsigned & SrcReg2,int & Mask,int & Value) const432 bool SystemZInstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
433 unsigned &SrcReg2, int &Mask,
434 int &Value) const {
435 assert(MI.isCompare() && "Caller should have checked for a comparison");
436
437 if (MI.getNumExplicitOperands() == 2 && MI.getOperand(0).isReg() &&
438 MI.getOperand(1).isImm()) {
439 SrcReg = MI.getOperand(0).getReg();
440 SrcReg2 = 0;
441 Value = MI.getOperand(1).getImm();
442 Mask = ~0;
443 return true;
444 }
445
446 return false;
447 }
448
449 // If Reg is a virtual register, return its definition, otherwise return null.
getDef(unsigned Reg,const MachineRegisterInfo * MRI)450 static MachineInstr *getDef(unsigned Reg,
451 const MachineRegisterInfo *MRI) {
452 if (TargetRegisterInfo::isPhysicalRegister(Reg))
453 return nullptr;
454 return MRI->getUniqueVRegDef(Reg);
455 }
456
457 // Return true if MI is a shift of type Opcode by Imm bits.
isShift(MachineInstr * MI,unsigned Opcode,int64_t Imm)458 static bool isShift(MachineInstr *MI, unsigned Opcode, int64_t Imm) {
459 return (MI->getOpcode() == Opcode &&
460 !MI->getOperand(2).getReg() &&
461 MI->getOperand(3).getImm() == Imm);
462 }
463
464 // If the destination of MI has no uses, delete it as dead.
eraseIfDead(MachineInstr * MI,const MachineRegisterInfo * MRI)465 static void eraseIfDead(MachineInstr *MI, const MachineRegisterInfo *MRI) {
466 if (MRI->use_nodbg_empty(MI->getOperand(0).getReg()))
467 MI->eraseFromParent();
468 }
469
470 // Compare compares SrcReg against zero. Check whether SrcReg contains
471 // the result of an IPM sequence whose input CC survives until Compare,
472 // and whether Compare is therefore redundant. Delete it and return
473 // true if so.
removeIPMBasedCompare(MachineInstr & Compare,unsigned SrcReg,const MachineRegisterInfo * MRI,const TargetRegisterInfo * TRI)474 static bool removeIPMBasedCompare(MachineInstr &Compare, unsigned SrcReg,
475 const MachineRegisterInfo *MRI,
476 const TargetRegisterInfo *TRI) {
477 MachineInstr *LGFR = nullptr;
478 MachineInstr *RLL = getDef(SrcReg, MRI);
479 if (RLL && RLL->getOpcode() == SystemZ::LGFR) {
480 LGFR = RLL;
481 RLL = getDef(LGFR->getOperand(1).getReg(), MRI);
482 }
483 if (!RLL || !isShift(RLL, SystemZ::RLL, 31))
484 return false;
485
486 MachineInstr *SRL = getDef(RLL->getOperand(1).getReg(), MRI);
487 if (!SRL || !isShift(SRL, SystemZ::SRL, SystemZ::IPM_CC))
488 return false;
489
490 MachineInstr *IPM = getDef(SRL->getOperand(1).getReg(), MRI);
491 if (!IPM || IPM->getOpcode() != SystemZ::IPM)
492 return false;
493
494 // Check that there are no assignments to CC between the IPM and Compare,
495 if (IPM->getParent() != Compare.getParent())
496 return false;
497 MachineBasicBlock::iterator MBBI = IPM, MBBE = Compare.getIterator();
498 for (++MBBI; MBBI != MBBE; ++MBBI) {
499 MachineInstr &MI = *MBBI;
500 if (MI.modifiesRegister(SystemZ::CC, TRI))
501 return false;
502 }
503
504 Compare.eraseFromParent();
505 if (LGFR)
506 eraseIfDead(LGFR, MRI);
507 eraseIfDead(RLL, MRI);
508 eraseIfDead(SRL, MRI);
509 eraseIfDead(IPM, MRI);
510
511 return true;
512 }
513
optimizeCompareInstr(MachineInstr & Compare,unsigned SrcReg,unsigned SrcReg2,int Mask,int Value,const MachineRegisterInfo * MRI) const514 bool SystemZInstrInfo::optimizeCompareInstr(
515 MachineInstr &Compare, unsigned SrcReg, unsigned SrcReg2, int Mask,
516 int Value, const MachineRegisterInfo *MRI) const {
517 assert(!SrcReg2 && "Only optimizing constant comparisons so far");
518 bool IsLogical = (Compare.getDesc().TSFlags & SystemZII::IsLogical) != 0;
519 return Value == 0 && !IsLogical &&
520 removeIPMBasedCompare(Compare, SrcReg, MRI, &RI);
521 }
522
523 // If Opcode is a move that has a conditional variant, return that variant,
524 // otherwise return 0.
getConditionalMove(unsigned Opcode)525 static unsigned getConditionalMove(unsigned Opcode) {
526 switch (Opcode) {
527 case SystemZ::LR: return SystemZ::LOCR;
528 case SystemZ::LGR: return SystemZ::LOCGR;
529 default: return 0;
530 }
531 }
532
getConditionalLoadImmediate(unsigned Opcode)533 static unsigned getConditionalLoadImmediate(unsigned Opcode) {
534 switch (Opcode) {
535 case SystemZ::LHI: return SystemZ::LOCHI;
536 case SystemZ::LGHI: return SystemZ::LOCGHI;
537 default: return 0;
538 }
539 }
540
isPredicable(MachineInstr & MI) const541 bool SystemZInstrInfo::isPredicable(MachineInstr &MI) const {
542 unsigned Opcode = MI.getOpcode();
543 if (STI.hasLoadStoreOnCond() && getConditionalMove(Opcode))
544 return true;
545 if (STI.hasLoadStoreOnCond2() && getConditionalLoadImmediate(Opcode))
546 return true;
547 if (Opcode == SystemZ::Return ||
548 Opcode == SystemZ::Trap ||
549 Opcode == SystemZ::CallJG ||
550 Opcode == SystemZ::CallBR)
551 return true;
552 return false;
553 }
554
555 bool SystemZInstrInfo::
isProfitableToIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,unsigned ExtraPredCycles,BranchProbability Probability) const556 isProfitableToIfCvt(MachineBasicBlock &MBB,
557 unsigned NumCycles, unsigned ExtraPredCycles,
558 BranchProbability Probability) const {
559 // Avoid using conditional returns at the end of a loop (since then
560 // we'd need to emit an unconditional branch to the beginning anyway,
561 // making the loop body longer). This doesn't apply for low-probability
562 // loops (eg. compare-and-swap retry), so just decide based on branch
563 // probability instead of looping structure.
564 // However, since Compare and Trap instructions cost the same as a regular
565 // Compare instruction, we should allow the if conversion to convert this
566 // into a Conditional Compare regardless of the branch probability.
567 if (MBB.getLastNonDebugInstr()->getOpcode() != SystemZ::Trap &&
568 MBB.succ_empty() && Probability < BranchProbability(1, 8))
569 return false;
570 // For now only convert single instructions.
571 return NumCycles == 1;
572 }
573
574 bool SystemZInstrInfo::
isProfitableToIfCvt(MachineBasicBlock & TMBB,unsigned NumCyclesT,unsigned ExtraPredCyclesT,MachineBasicBlock & FMBB,unsigned NumCyclesF,unsigned ExtraPredCyclesF,BranchProbability Probability) const575 isProfitableToIfCvt(MachineBasicBlock &TMBB,
576 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
577 MachineBasicBlock &FMBB,
578 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
579 BranchProbability Probability) const {
580 // For now avoid converting mutually-exclusive cases.
581 return false;
582 }
583
584 bool SystemZInstrInfo::
isProfitableToDupForIfCvt(MachineBasicBlock & MBB,unsigned NumCycles,BranchProbability Probability) const585 isProfitableToDupForIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
586 BranchProbability Probability) const {
587 // For now only duplicate single instructions.
588 return NumCycles == 1;
589 }
590
PredicateInstruction(MachineInstr & MI,ArrayRef<MachineOperand> Pred) const591 bool SystemZInstrInfo::PredicateInstruction(
592 MachineInstr &MI, ArrayRef<MachineOperand> Pred) const {
593 assert(Pred.size() == 2 && "Invalid condition");
594 unsigned CCValid = Pred[0].getImm();
595 unsigned CCMask = Pred[1].getImm();
596 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
597 unsigned Opcode = MI.getOpcode();
598 if (STI.hasLoadStoreOnCond()) {
599 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
600 MI.setDesc(get(CondOpcode));
601 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
602 .addImm(CCValid)
603 .addImm(CCMask)
604 .addReg(SystemZ::CC, RegState::Implicit);
605 return true;
606 }
607 }
608 if (STI.hasLoadStoreOnCond2()) {
609 if (unsigned CondOpcode = getConditionalLoadImmediate(Opcode)) {
610 MI.setDesc(get(CondOpcode));
611 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
612 .addImm(CCValid)
613 .addImm(CCMask)
614 .addReg(SystemZ::CC, RegState::Implicit);
615 return true;
616 }
617 }
618 if (Opcode == SystemZ::Trap) {
619 MI.setDesc(get(SystemZ::CondTrap));
620 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
621 .addImm(CCValid).addImm(CCMask)
622 .addReg(SystemZ::CC, RegState::Implicit);
623 return true;
624 }
625 if (Opcode == SystemZ::Return) {
626 MI.setDesc(get(SystemZ::CondReturn));
627 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
628 .addImm(CCValid).addImm(CCMask)
629 .addReg(SystemZ::CC, RegState::Implicit);
630 return true;
631 }
632 if (Opcode == SystemZ::CallJG) {
633 MachineOperand FirstOp = MI.getOperand(0);
634 const uint32_t *RegMask = MI.getOperand(1).getRegMask();
635 MI.RemoveOperand(1);
636 MI.RemoveOperand(0);
637 MI.setDesc(get(SystemZ::CallBRCL));
638 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
639 .addImm(CCValid).addImm(CCMask)
640 .addOperand(FirstOp)
641 .addRegMask(RegMask)
642 .addReg(SystemZ::CC, RegState::Implicit);
643 return true;
644 }
645 if (Opcode == SystemZ::CallBR) {
646 const uint32_t *RegMask = MI.getOperand(0).getRegMask();
647 MI.RemoveOperand(0);
648 MI.setDesc(get(SystemZ::CallBCR));
649 MachineInstrBuilder(*MI.getParent()->getParent(), MI)
650 .addImm(CCValid).addImm(CCMask)
651 .addRegMask(RegMask)
652 .addReg(SystemZ::CC, RegState::Implicit);
653 return true;
654 }
655 return false;
656 }
657
copyPhysReg(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,const DebugLoc & DL,unsigned DestReg,unsigned SrcReg,bool KillSrc) const658 void SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
659 MachineBasicBlock::iterator MBBI,
660 const DebugLoc &DL, unsigned DestReg,
661 unsigned SrcReg, bool KillSrc) const {
662 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
663 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
664 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_h64),
665 RI.getSubReg(SrcReg, SystemZ::subreg_h64), KillSrc);
666 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_l64),
667 RI.getSubReg(SrcReg, SystemZ::subreg_l64), KillSrc);
668 return;
669 }
670
671 if (SystemZ::GRX32BitRegClass.contains(DestReg, SrcReg)) {
672 emitGRX32Move(MBB, MBBI, DL, DestReg, SrcReg, SystemZ::LR, 32, KillSrc);
673 return;
674 }
675
676 // Everything else needs only one instruction.
677 unsigned Opcode;
678 if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
679 Opcode = SystemZ::LGR;
680 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
681 // For z13 we prefer LDR over LER to avoid partial register dependencies.
682 Opcode = STI.hasVector() ? SystemZ::LDR32 : SystemZ::LER;
683 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
684 Opcode = SystemZ::LDR;
685 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
686 Opcode = SystemZ::LXR;
687 else if (SystemZ::VR32BitRegClass.contains(DestReg, SrcReg))
688 Opcode = SystemZ::VLR32;
689 else if (SystemZ::VR64BitRegClass.contains(DestReg, SrcReg))
690 Opcode = SystemZ::VLR64;
691 else if (SystemZ::VR128BitRegClass.contains(DestReg, SrcReg))
692 Opcode = SystemZ::VLR;
693 else
694 llvm_unreachable("Impossible reg-to-reg copy");
695
696 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
697 .addReg(SrcReg, getKillRegState(KillSrc));
698 }
699
storeRegToStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,unsigned SrcReg,bool isKill,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const700 void SystemZInstrInfo::storeRegToStackSlot(
701 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned SrcReg,
702 bool isKill, int FrameIdx, const TargetRegisterClass *RC,
703 const TargetRegisterInfo *TRI) const {
704 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
705
706 // Callers may expect a single instruction, so keep 128-bit moves
707 // together for now and lower them after register allocation.
708 unsigned LoadOpcode, StoreOpcode;
709 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
710 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
711 .addReg(SrcReg, getKillRegState(isKill)),
712 FrameIdx);
713 }
714
loadRegFromStackSlot(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,unsigned DestReg,int FrameIdx,const TargetRegisterClass * RC,const TargetRegisterInfo * TRI) const715 void SystemZInstrInfo::loadRegFromStackSlot(
716 MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI, unsigned DestReg,
717 int FrameIdx, const TargetRegisterClass *RC,
718 const TargetRegisterInfo *TRI) const {
719 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
720
721 // Callers may expect a single instruction, so keep 128-bit moves
722 // together for now and lower them after register allocation.
723 unsigned LoadOpcode, StoreOpcode;
724 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
725 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
726 FrameIdx);
727 }
728
729 // Return true if MI is a simple load or store with a 12-bit displacement
730 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
isSimpleBD12Move(const MachineInstr * MI,unsigned Flag)731 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
732 const MCInstrDesc &MCID = MI->getDesc();
733 return ((MCID.TSFlags & Flag) &&
734 isUInt<12>(MI->getOperand(2).getImm()) &&
735 MI->getOperand(3).getReg() == 0);
736 }
737
738 namespace {
739 struct LogicOp {
LogicOp__anon4bf2ff270111::LogicOp740 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
LogicOp__anon4bf2ff270111::LogicOp741 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
742 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
743
operator bool__anon4bf2ff270111::LogicOp744 explicit operator bool() const { return RegSize; }
745
746 unsigned RegSize, ImmLSB, ImmSize;
747 };
748 } // end anonymous namespace
749
interpretAndImmediate(unsigned Opcode)750 static LogicOp interpretAndImmediate(unsigned Opcode) {
751 switch (Opcode) {
752 case SystemZ::NILMux: return LogicOp(32, 0, 16);
753 case SystemZ::NIHMux: return LogicOp(32, 16, 16);
754 case SystemZ::NILL64: return LogicOp(64, 0, 16);
755 case SystemZ::NILH64: return LogicOp(64, 16, 16);
756 case SystemZ::NIHL64: return LogicOp(64, 32, 16);
757 case SystemZ::NIHH64: return LogicOp(64, 48, 16);
758 case SystemZ::NIFMux: return LogicOp(32, 0, 32);
759 case SystemZ::NILF64: return LogicOp(64, 0, 32);
760 case SystemZ::NIHF64: return LogicOp(64, 32, 32);
761 default: return LogicOp();
762 }
763 }
764
transferDeadCC(MachineInstr * OldMI,MachineInstr * NewMI)765 static void transferDeadCC(MachineInstr *OldMI, MachineInstr *NewMI) {
766 if (OldMI->registerDefIsDead(SystemZ::CC)) {
767 MachineOperand *CCDef = NewMI->findRegisterDefOperand(SystemZ::CC);
768 if (CCDef != nullptr)
769 CCDef->setIsDead(true);
770 }
771 }
772
773 // Used to return from convertToThreeAddress after replacing two-address
774 // instruction OldMI with three-address instruction NewMI.
finishConvertToThreeAddress(MachineInstr * OldMI,MachineInstr * NewMI,LiveVariables * LV)775 static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
776 MachineInstr *NewMI,
777 LiveVariables *LV) {
778 if (LV) {
779 unsigned NumOps = OldMI->getNumOperands();
780 for (unsigned I = 1; I < NumOps; ++I) {
781 MachineOperand &Op = OldMI->getOperand(I);
782 if (Op.isReg() && Op.isKill())
783 LV->replaceKillInstruction(Op.getReg(), *OldMI, *NewMI);
784 }
785 }
786 transferDeadCC(OldMI, NewMI);
787 return NewMI;
788 }
789
convertToThreeAddress(MachineFunction::iterator & MFI,MachineInstr & MI,LiveVariables * LV) const790 MachineInstr *SystemZInstrInfo::convertToThreeAddress(
791 MachineFunction::iterator &MFI, MachineInstr &MI, LiveVariables *LV) const {
792 MachineBasicBlock *MBB = MI.getParent();
793 MachineFunction *MF = MBB->getParent();
794 MachineRegisterInfo &MRI = MF->getRegInfo();
795
796 unsigned Opcode = MI.getOpcode();
797 unsigned NumOps = MI.getNumOperands();
798
799 // Try to convert something like SLL into SLLK, if supported.
800 // We prefer to keep the two-operand form where possible both
801 // because it tends to be shorter and because some instructions
802 // have memory forms that can be used during spilling.
803 if (STI.hasDistinctOps()) {
804 MachineOperand &Dest = MI.getOperand(0);
805 MachineOperand &Src = MI.getOperand(1);
806 unsigned DestReg = Dest.getReg();
807 unsigned SrcReg = Src.getReg();
808 // AHIMux is only really a three-operand instruction when both operands
809 // are low registers. Try to constrain both operands to be low if
810 // possible.
811 if (Opcode == SystemZ::AHIMux &&
812 TargetRegisterInfo::isVirtualRegister(DestReg) &&
813 TargetRegisterInfo::isVirtualRegister(SrcReg) &&
814 MRI.getRegClass(DestReg)->contains(SystemZ::R1L) &&
815 MRI.getRegClass(SrcReg)->contains(SystemZ::R1L)) {
816 MRI.constrainRegClass(DestReg, &SystemZ::GR32BitRegClass);
817 MRI.constrainRegClass(SrcReg, &SystemZ::GR32BitRegClass);
818 }
819 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
820 if (ThreeOperandOpcode >= 0) {
821 // Create three address instruction without adding the implicit
822 // operands. Those will instead be copied over from the original
823 // instruction by the loop below.
824 MachineInstrBuilder MIB(
825 *MF, MF->CreateMachineInstr(get(ThreeOperandOpcode), MI.getDebugLoc(),
826 /*NoImplicit=*/true));
827 MIB.addOperand(Dest);
828 // Keep the kill state, but drop the tied flag.
829 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
830 // Keep the remaining operands as-is.
831 for (unsigned I = 2; I < NumOps; ++I)
832 MIB.addOperand(MI.getOperand(I));
833 MBB->insert(MI, MIB);
834 return finishConvertToThreeAddress(&MI, MIB, LV);
835 }
836 }
837
838 // Try to convert an AND into an RISBG-type instruction.
839 if (LogicOp And = interpretAndImmediate(Opcode)) {
840 uint64_t Imm = MI.getOperand(2).getImm() << And.ImmLSB;
841 // AND IMMEDIATE leaves the other bits of the register unchanged.
842 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
843 unsigned Start, End;
844 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
845 unsigned NewOpcode;
846 if (And.RegSize == 64) {
847 NewOpcode = SystemZ::RISBG;
848 // Prefer RISBGN if available, since it does not clobber CC.
849 if (STI.hasMiscellaneousExtensions())
850 NewOpcode = SystemZ::RISBGN;
851 } else {
852 NewOpcode = SystemZ::RISBMux;
853 Start &= 31;
854 End &= 31;
855 }
856 MachineOperand &Dest = MI.getOperand(0);
857 MachineOperand &Src = MI.getOperand(1);
858 MachineInstrBuilder MIB =
859 BuildMI(*MBB, MI, MI.getDebugLoc(), get(NewOpcode))
860 .addOperand(Dest)
861 .addReg(0)
862 .addReg(Src.getReg(), getKillRegState(Src.isKill()),
863 Src.getSubReg())
864 .addImm(Start)
865 .addImm(End + 128)
866 .addImm(0);
867 return finishConvertToThreeAddress(&MI, MIB, LV);
868 }
869 }
870 return nullptr;
871 }
872
foldMemoryOperandImpl(MachineFunction & MF,MachineInstr & MI,ArrayRef<unsigned> Ops,MachineBasicBlock::iterator InsertPt,int FrameIndex,LiveIntervals * LIS) const873 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
874 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
875 MachineBasicBlock::iterator InsertPt, int FrameIndex,
876 LiveIntervals *LIS) const {
877 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
878 const MachineFrameInfo *MFI = MF.getFrameInfo();
879 unsigned Size = MFI->getObjectSize(FrameIndex);
880 unsigned Opcode = MI.getOpcode();
881
882 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
883 if (LIS != nullptr && (Opcode == SystemZ::LA || Opcode == SystemZ::LAY) &&
884 isInt<8>(MI.getOperand(2).getImm()) && !MI.getOperand(3).getReg()) {
885
886 // Check CC liveness, since new instruction introduces a dead
887 // def of CC.
888 MCRegUnitIterator CCUnit(SystemZ::CC, TRI);
889 LiveRange &CCLiveRange = LIS->getRegUnit(*CCUnit);
890 ++CCUnit;
891 assert (!CCUnit.isValid() && "CC only has one reg unit.");
892 SlotIndex MISlot =
893 LIS->getSlotIndexes()->getInstructionIndex(MI).getRegSlot();
894 if (!CCLiveRange.liveAt(MISlot)) {
895 // LA(Y) %reg, CONST(%reg) -> AGSI %mem, CONST
896 MachineInstr *BuiltMI = BuildMI(*InsertPt->getParent(), InsertPt,
897 MI.getDebugLoc(), get(SystemZ::AGSI))
898 .addFrameIndex(FrameIndex)
899 .addImm(0)
900 .addImm(MI.getOperand(2).getImm());
901 BuiltMI->findRegisterDefOperand(SystemZ::CC)->setIsDead(true);
902 CCLiveRange.createDeadDef(MISlot, LIS->getVNInfoAllocator());
903 return BuiltMI;
904 }
905 }
906 return nullptr;
907 }
908
909 // All other cases require a single operand.
910 if (Ops.size() != 1)
911 return nullptr;
912
913 unsigned OpNum = Ops[0];
914 assert(Size ==
915 MF.getRegInfo()
916 .getRegClass(MI.getOperand(OpNum).getReg())
917 ->getSize() &&
918 "Invalid size combination");
919
920 if ((Opcode == SystemZ::AHI || Opcode == SystemZ::AGHI) && OpNum == 0 &&
921 isInt<8>(MI.getOperand(2).getImm())) {
922 // A(G)HI %reg, CONST -> A(G)SI %mem, CONST
923 Opcode = (Opcode == SystemZ::AHI ? SystemZ::ASI : SystemZ::AGSI);
924 MachineInstr *BuiltMI =
925 BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(), get(Opcode))
926 .addFrameIndex(FrameIndex)
927 .addImm(0)
928 .addImm(MI.getOperand(2).getImm());
929 transferDeadCC(&MI, BuiltMI);
930 return BuiltMI;
931 }
932
933 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
934 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
935 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
936 // If we're spilling the destination of an LDGR or LGDR, store the
937 // source register instead.
938 if (OpNum == 0) {
939 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
940 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
941 get(StoreOpcode))
942 .addOperand(MI.getOperand(1))
943 .addFrameIndex(FrameIndex)
944 .addImm(0)
945 .addReg(0);
946 }
947 // If we're spilling the source of an LDGR or LGDR, load the
948 // destination register instead.
949 if (OpNum == 1) {
950 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
951 unsigned Dest = MI.getOperand(0).getReg();
952 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
953 get(LoadOpcode), Dest)
954 .addFrameIndex(FrameIndex)
955 .addImm(0)
956 .addReg(0);
957 }
958 }
959
960 // Look for cases where the source of a simple store or the destination
961 // of a simple load is being spilled. Try to use MVC instead.
962 //
963 // Although MVC is in practice a fast choice in these cases, it is still
964 // logically a bytewise copy. This means that we cannot use it if the
965 // load or store is volatile. We also wouldn't be able to use MVC if
966 // the two memories partially overlap, but that case cannot occur here,
967 // because we know that one of the memories is a full frame index.
968 //
969 // For performance reasons, we also want to avoid using MVC if the addresses
970 // might be equal. We don't worry about that case here, because spill slot
971 // coloring happens later, and because we have special code to remove
972 // MVCs that turn out to be redundant.
973 if (OpNum == 0 && MI.hasOneMemOperand()) {
974 MachineMemOperand *MMO = *MI.memoperands_begin();
975 if (MMO->getSize() == Size && !MMO->isVolatile()) {
976 // Handle conversion of loads.
977 if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXLoad)) {
978 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
979 get(SystemZ::MVC))
980 .addFrameIndex(FrameIndex)
981 .addImm(0)
982 .addImm(Size)
983 .addOperand(MI.getOperand(1))
984 .addImm(MI.getOperand(2).getImm())
985 .addMemOperand(MMO);
986 }
987 // Handle conversion of stores.
988 if (isSimpleBD12Move(&MI, SystemZII::SimpleBDXStore)) {
989 return BuildMI(*InsertPt->getParent(), InsertPt, MI.getDebugLoc(),
990 get(SystemZ::MVC))
991 .addOperand(MI.getOperand(1))
992 .addImm(MI.getOperand(2).getImm())
993 .addImm(Size)
994 .addFrameIndex(FrameIndex)
995 .addImm(0)
996 .addMemOperand(MMO);
997 }
998 }
999 }
1000
1001 // If the spilled operand is the final one, try to change <INSN>R
1002 // into <INSN>.
1003 int MemOpcode = SystemZ::getMemOpcode(Opcode);
1004 if (MemOpcode >= 0) {
1005 unsigned NumOps = MI.getNumExplicitOperands();
1006 if (OpNum == NumOps - 1) {
1007 const MCInstrDesc &MemDesc = get(MemOpcode);
1008 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
1009 assert(AccessBytes != 0 && "Size of access should be known");
1010 assert(AccessBytes <= Size && "Access outside the frame index");
1011 uint64_t Offset = Size - AccessBytes;
1012 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
1013 MI.getDebugLoc(), get(MemOpcode));
1014 for (unsigned I = 0; I < OpNum; ++I)
1015 MIB.addOperand(MI.getOperand(I));
1016 MIB.addFrameIndex(FrameIndex).addImm(Offset);
1017 if (MemDesc.TSFlags & SystemZII::HasIndex)
1018 MIB.addReg(0);
1019 transferDeadCC(&MI, MIB);
1020 return MIB;
1021 }
1022 }
1023
1024 return nullptr;
1025 }
1026
foldMemoryOperandImpl(MachineFunction & MF,MachineInstr & MI,ArrayRef<unsigned> Ops,MachineBasicBlock::iterator InsertPt,MachineInstr & LoadMI,LiveIntervals * LIS) const1027 MachineInstr *SystemZInstrInfo::foldMemoryOperandImpl(
1028 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
1029 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
1030 LiveIntervals *LIS) const {
1031 return nullptr;
1032 }
1033
expandPostRAPseudo(MachineInstr & MI) const1034 bool SystemZInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
1035 switch (MI.getOpcode()) {
1036 case SystemZ::L128:
1037 splitMove(MI, SystemZ::LG);
1038 return true;
1039
1040 case SystemZ::ST128:
1041 splitMove(MI, SystemZ::STG);
1042 return true;
1043
1044 case SystemZ::LX:
1045 splitMove(MI, SystemZ::LD);
1046 return true;
1047
1048 case SystemZ::STX:
1049 splitMove(MI, SystemZ::STD);
1050 return true;
1051
1052 case SystemZ::LBMux:
1053 expandRXYPseudo(MI, SystemZ::LB, SystemZ::LBH);
1054 return true;
1055
1056 case SystemZ::LHMux:
1057 expandRXYPseudo(MI, SystemZ::LH, SystemZ::LHH);
1058 return true;
1059
1060 case SystemZ::LLCRMux:
1061 expandZExtPseudo(MI, SystemZ::LLCR, 8);
1062 return true;
1063
1064 case SystemZ::LLHRMux:
1065 expandZExtPseudo(MI, SystemZ::LLHR, 16);
1066 return true;
1067
1068 case SystemZ::LLCMux:
1069 expandRXYPseudo(MI, SystemZ::LLC, SystemZ::LLCH);
1070 return true;
1071
1072 case SystemZ::LLHMux:
1073 expandRXYPseudo(MI, SystemZ::LLH, SystemZ::LLHH);
1074 return true;
1075
1076 case SystemZ::LMux:
1077 expandRXYPseudo(MI, SystemZ::L, SystemZ::LFH);
1078 return true;
1079
1080 case SystemZ::STCMux:
1081 expandRXYPseudo(MI, SystemZ::STC, SystemZ::STCH);
1082 return true;
1083
1084 case SystemZ::STHMux:
1085 expandRXYPseudo(MI, SystemZ::STH, SystemZ::STHH);
1086 return true;
1087
1088 case SystemZ::STMux:
1089 expandRXYPseudo(MI, SystemZ::ST, SystemZ::STFH);
1090 return true;
1091
1092 case SystemZ::LHIMux:
1093 expandRIPseudo(MI, SystemZ::LHI, SystemZ::IIHF, true);
1094 return true;
1095
1096 case SystemZ::IIFMux:
1097 expandRIPseudo(MI, SystemZ::IILF, SystemZ::IIHF, false);
1098 return true;
1099
1100 case SystemZ::IILMux:
1101 expandRIPseudo(MI, SystemZ::IILL, SystemZ::IIHL, false);
1102 return true;
1103
1104 case SystemZ::IIHMux:
1105 expandRIPseudo(MI, SystemZ::IILH, SystemZ::IIHH, false);
1106 return true;
1107
1108 case SystemZ::NIFMux:
1109 expandRIPseudo(MI, SystemZ::NILF, SystemZ::NIHF, false);
1110 return true;
1111
1112 case SystemZ::NILMux:
1113 expandRIPseudo(MI, SystemZ::NILL, SystemZ::NIHL, false);
1114 return true;
1115
1116 case SystemZ::NIHMux:
1117 expandRIPseudo(MI, SystemZ::NILH, SystemZ::NIHH, false);
1118 return true;
1119
1120 case SystemZ::OIFMux:
1121 expandRIPseudo(MI, SystemZ::OILF, SystemZ::OIHF, false);
1122 return true;
1123
1124 case SystemZ::OILMux:
1125 expandRIPseudo(MI, SystemZ::OILL, SystemZ::OIHL, false);
1126 return true;
1127
1128 case SystemZ::OIHMux:
1129 expandRIPseudo(MI, SystemZ::OILH, SystemZ::OIHH, false);
1130 return true;
1131
1132 case SystemZ::XIFMux:
1133 expandRIPseudo(MI, SystemZ::XILF, SystemZ::XIHF, false);
1134 return true;
1135
1136 case SystemZ::TMLMux:
1137 expandRIPseudo(MI, SystemZ::TMLL, SystemZ::TMHL, false);
1138 return true;
1139
1140 case SystemZ::TMHMux:
1141 expandRIPseudo(MI, SystemZ::TMLH, SystemZ::TMHH, false);
1142 return true;
1143
1144 case SystemZ::AHIMux:
1145 expandRIPseudo(MI, SystemZ::AHI, SystemZ::AIH, false);
1146 return true;
1147
1148 case SystemZ::AHIMuxK:
1149 expandRIEPseudo(MI, SystemZ::AHI, SystemZ::AHIK, SystemZ::AIH);
1150 return true;
1151
1152 case SystemZ::AFIMux:
1153 expandRIPseudo(MI, SystemZ::AFI, SystemZ::AIH, false);
1154 return true;
1155
1156 case SystemZ::CFIMux:
1157 expandRIPseudo(MI, SystemZ::CFI, SystemZ::CIH, false);
1158 return true;
1159
1160 case SystemZ::CLFIMux:
1161 expandRIPseudo(MI, SystemZ::CLFI, SystemZ::CLIH, false);
1162 return true;
1163
1164 case SystemZ::CMux:
1165 expandRXYPseudo(MI, SystemZ::C, SystemZ::CHF);
1166 return true;
1167
1168 case SystemZ::CLMux:
1169 expandRXYPseudo(MI, SystemZ::CL, SystemZ::CLHF);
1170 return true;
1171
1172 case SystemZ::RISBMux: {
1173 bool DestIsHigh = isHighReg(MI.getOperand(0).getReg());
1174 bool SrcIsHigh = isHighReg(MI.getOperand(2).getReg());
1175 if (SrcIsHigh == DestIsHigh)
1176 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHH : SystemZ::RISBLL));
1177 else {
1178 MI.setDesc(get(DestIsHigh ? SystemZ::RISBHL : SystemZ::RISBLH));
1179 MI.getOperand(5).setImm(MI.getOperand(5).getImm() ^ 32);
1180 }
1181 return true;
1182 }
1183
1184 case SystemZ::ADJDYNALLOC:
1185 splitAdjDynAlloc(MI);
1186 return true;
1187
1188 case TargetOpcode::LOAD_STACK_GUARD:
1189 expandLoadStackGuard(&MI);
1190 return true;
1191
1192 default:
1193 return false;
1194 }
1195 }
1196
getInstSizeInBytes(const MachineInstr & MI) const1197 uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr &MI) const {
1198 if (MI.getOpcode() == TargetOpcode::INLINEASM) {
1199 const MachineFunction *MF = MI.getParent()->getParent();
1200 const char *AsmStr = MI.getOperand(0).getSymbolName();
1201 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
1202 }
1203 return MI.getDesc().getSize();
1204 }
1205
1206 SystemZII::Branch
getBranchInfo(const MachineInstr & MI) const1207 SystemZInstrInfo::getBranchInfo(const MachineInstr &MI) const {
1208 switch (MI.getOpcode()) {
1209 case SystemZ::BR:
1210 case SystemZ::J:
1211 case SystemZ::JG:
1212 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
1213 SystemZ::CCMASK_ANY, &MI.getOperand(0));
1214
1215 case SystemZ::BRC:
1216 case SystemZ::BRCL:
1217 return SystemZII::Branch(SystemZII::BranchNormal, MI.getOperand(0).getImm(),
1218 MI.getOperand(1).getImm(), &MI.getOperand(2));
1219
1220 case SystemZ::BRCT:
1221 return SystemZII::Branch(SystemZII::BranchCT, SystemZ::CCMASK_ICMP,
1222 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1223
1224 case SystemZ::BRCTG:
1225 return SystemZII::Branch(SystemZII::BranchCTG, SystemZ::CCMASK_ICMP,
1226 SystemZ::CCMASK_CMP_NE, &MI.getOperand(2));
1227
1228 case SystemZ::CIJ:
1229 case SystemZ::CRJ:
1230 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
1231 MI.getOperand(2).getImm(), &MI.getOperand(3));
1232
1233 case SystemZ::CLIJ:
1234 case SystemZ::CLRJ:
1235 return SystemZII::Branch(SystemZII::BranchCL, SystemZ::CCMASK_ICMP,
1236 MI.getOperand(2).getImm(), &MI.getOperand(3));
1237
1238 case SystemZ::CGIJ:
1239 case SystemZ::CGRJ:
1240 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
1241 MI.getOperand(2).getImm(), &MI.getOperand(3));
1242
1243 case SystemZ::CLGIJ:
1244 case SystemZ::CLGRJ:
1245 return SystemZII::Branch(SystemZII::BranchCLG, SystemZ::CCMASK_ICMP,
1246 MI.getOperand(2).getImm(), &MI.getOperand(3));
1247
1248 default:
1249 llvm_unreachable("Unrecognized branch opcode");
1250 }
1251 }
1252
getLoadStoreOpcodes(const TargetRegisterClass * RC,unsigned & LoadOpcode,unsigned & StoreOpcode) const1253 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
1254 unsigned &LoadOpcode,
1255 unsigned &StoreOpcode) const {
1256 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
1257 LoadOpcode = SystemZ::L;
1258 StoreOpcode = SystemZ::ST;
1259 } else if (RC == &SystemZ::GRH32BitRegClass) {
1260 LoadOpcode = SystemZ::LFH;
1261 StoreOpcode = SystemZ::STFH;
1262 } else if (RC == &SystemZ::GRX32BitRegClass) {
1263 LoadOpcode = SystemZ::LMux;
1264 StoreOpcode = SystemZ::STMux;
1265 } else if (RC == &SystemZ::GR64BitRegClass ||
1266 RC == &SystemZ::ADDR64BitRegClass) {
1267 LoadOpcode = SystemZ::LG;
1268 StoreOpcode = SystemZ::STG;
1269 } else if (RC == &SystemZ::GR128BitRegClass ||
1270 RC == &SystemZ::ADDR128BitRegClass) {
1271 LoadOpcode = SystemZ::L128;
1272 StoreOpcode = SystemZ::ST128;
1273 } else if (RC == &SystemZ::FP32BitRegClass) {
1274 LoadOpcode = SystemZ::LE;
1275 StoreOpcode = SystemZ::STE;
1276 } else if (RC == &SystemZ::FP64BitRegClass) {
1277 LoadOpcode = SystemZ::LD;
1278 StoreOpcode = SystemZ::STD;
1279 } else if (RC == &SystemZ::FP128BitRegClass) {
1280 LoadOpcode = SystemZ::LX;
1281 StoreOpcode = SystemZ::STX;
1282 } else if (RC == &SystemZ::VR32BitRegClass) {
1283 LoadOpcode = SystemZ::VL32;
1284 StoreOpcode = SystemZ::VST32;
1285 } else if (RC == &SystemZ::VR64BitRegClass) {
1286 LoadOpcode = SystemZ::VL64;
1287 StoreOpcode = SystemZ::VST64;
1288 } else if (RC == &SystemZ::VF128BitRegClass ||
1289 RC == &SystemZ::VR128BitRegClass) {
1290 LoadOpcode = SystemZ::VL;
1291 StoreOpcode = SystemZ::VST;
1292 } else
1293 llvm_unreachable("Unsupported regclass to load or store");
1294 }
1295
getOpcodeForOffset(unsigned Opcode,int64_t Offset) const1296 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
1297 int64_t Offset) const {
1298 const MCInstrDesc &MCID = get(Opcode);
1299 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
1300 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
1301 // Get the instruction to use for unsigned 12-bit displacements.
1302 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
1303 if (Disp12Opcode >= 0)
1304 return Disp12Opcode;
1305
1306 // All address-related instructions can use unsigned 12-bit
1307 // displacements.
1308 return Opcode;
1309 }
1310 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
1311 // Get the instruction to use for signed 20-bit displacements.
1312 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
1313 if (Disp20Opcode >= 0)
1314 return Disp20Opcode;
1315
1316 // Check whether Opcode allows signed 20-bit displacements.
1317 if (MCID.TSFlags & SystemZII::Has20BitOffset)
1318 return Opcode;
1319 }
1320 return 0;
1321 }
1322
getLoadAndTest(unsigned Opcode) const1323 unsigned SystemZInstrInfo::getLoadAndTest(unsigned Opcode) const {
1324 switch (Opcode) {
1325 case SystemZ::L: return SystemZ::LT;
1326 case SystemZ::LY: return SystemZ::LT;
1327 case SystemZ::LG: return SystemZ::LTG;
1328 case SystemZ::LGF: return SystemZ::LTGF;
1329 case SystemZ::LR: return SystemZ::LTR;
1330 case SystemZ::LGFR: return SystemZ::LTGFR;
1331 case SystemZ::LGR: return SystemZ::LTGR;
1332 case SystemZ::LER: return SystemZ::LTEBR;
1333 case SystemZ::LDR: return SystemZ::LTDBR;
1334 case SystemZ::LXR: return SystemZ::LTXBR;
1335 case SystemZ::LCDFR: return SystemZ::LCDBR;
1336 case SystemZ::LPDFR: return SystemZ::LPDBR;
1337 case SystemZ::LNDFR: return SystemZ::LNDBR;
1338 case SystemZ::LCDFR_32: return SystemZ::LCEBR;
1339 case SystemZ::LPDFR_32: return SystemZ::LPEBR;
1340 case SystemZ::LNDFR_32: return SystemZ::LNEBR;
1341 // On zEC12 we prefer to use RISBGN. But if there is a chance to
1342 // actually use the condition code, we may turn it back into RISGB.
1343 // Note that RISBG is not really a "load-and-test" instruction,
1344 // but sets the same condition code values, so is OK to use here.
1345 case SystemZ::RISBGN: return SystemZ::RISBG;
1346 default: return 0;
1347 }
1348 }
1349
1350 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
1351 // have already been filtered out. Store the first set bit in LSB and
1352 // the number of set bits in Length if so.
isStringOfOnes(uint64_t Mask,unsigned & LSB,unsigned & Length)1353 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
1354 unsigned First = findFirstSet(Mask);
1355 uint64_t Top = (Mask >> First) + 1;
1356 if ((Top & -Top) == Top) {
1357 LSB = First;
1358 Length = findFirstSet(Top);
1359 return true;
1360 }
1361 return false;
1362 }
1363
isRxSBGMask(uint64_t Mask,unsigned BitSize,unsigned & Start,unsigned & End) const1364 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
1365 unsigned &Start, unsigned &End) const {
1366 // Reject trivial all-zero masks.
1367 Mask &= allOnes(BitSize);
1368 if (Mask == 0)
1369 return false;
1370
1371 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
1372 // the msb and End specifies the index of the lsb.
1373 unsigned LSB, Length;
1374 if (isStringOfOnes(Mask, LSB, Length)) {
1375 Start = 63 - (LSB + Length - 1);
1376 End = 63 - LSB;
1377 return true;
1378 }
1379
1380 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
1381 // of the low 1s and End specifies the lsb of the high 1s.
1382 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
1383 assert(LSB > 0 && "Bottom bit must be set");
1384 assert(LSB + Length < BitSize && "Top bit must be set");
1385 Start = 63 - (LSB - 1);
1386 End = 63 - (LSB + Length);
1387 return true;
1388 }
1389
1390 return false;
1391 }
1392
getFusedCompare(unsigned Opcode,SystemZII::FusedCompareType Type,const MachineInstr * MI) const1393 unsigned SystemZInstrInfo::getFusedCompare(unsigned Opcode,
1394 SystemZII::FusedCompareType Type,
1395 const MachineInstr *MI) const {
1396 switch (Opcode) {
1397 case SystemZ::CHI:
1398 case SystemZ::CGHI:
1399 if (!(MI && isInt<8>(MI->getOperand(1).getImm())))
1400 return 0;
1401 break;
1402 case SystemZ::CLFI:
1403 case SystemZ::CLGFI:
1404 if (!(MI && isUInt<8>(MI->getOperand(1).getImm())))
1405 return 0;
1406 }
1407 switch (Type) {
1408 case SystemZII::CompareAndBranch:
1409 switch (Opcode) {
1410 case SystemZ::CR:
1411 return SystemZ::CRJ;
1412 case SystemZ::CGR:
1413 return SystemZ::CGRJ;
1414 case SystemZ::CHI:
1415 return SystemZ::CIJ;
1416 case SystemZ::CGHI:
1417 return SystemZ::CGIJ;
1418 case SystemZ::CLR:
1419 return SystemZ::CLRJ;
1420 case SystemZ::CLGR:
1421 return SystemZ::CLGRJ;
1422 case SystemZ::CLFI:
1423 return SystemZ::CLIJ;
1424 case SystemZ::CLGFI:
1425 return SystemZ::CLGIJ;
1426 default:
1427 return 0;
1428 }
1429 case SystemZII::CompareAndReturn:
1430 switch (Opcode) {
1431 case SystemZ::CR:
1432 return SystemZ::CRBReturn;
1433 case SystemZ::CGR:
1434 return SystemZ::CGRBReturn;
1435 case SystemZ::CHI:
1436 return SystemZ::CIBReturn;
1437 case SystemZ::CGHI:
1438 return SystemZ::CGIBReturn;
1439 case SystemZ::CLR:
1440 return SystemZ::CLRBReturn;
1441 case SystemZ::CLGR:
1442 return SystemZ::CLGRBReturn;
1443 case SystemZ::CLFI:
1444 return SystemZ::CLIBReturn;
1445 case SystemZ::CLGFI:
1446 return SystemZ::CLGIBReturn;
1447 default:
1448 return 0;
1449 }
1450 case SystemZII::CompareAndSibcall:
1451 switch (Opcode) {
1452 case SystemZ::CR:
1453 return SystemZ::CRBCall;
1454 case SystemZ::CGR:
1455 return SystemZ::CGRBCall;
1456 case SystemZ::CHI:
1457 return SystemZ::CIBCall;
1458 case SystemZ::CGHI:
1459 return SystemZ::CGIBCall;
1460 case SystemZ::CLR:
1461 return SystemZ::CLRBCall;
1462 case SystemZ::CLGR:
1463 return SystemZ::CLGRBCall;
1464 case SystemZ::CLFI:
1465 return SystemZ::CLIBCall;
1466 case SystemZ::CLGFI:
1467 return SystemZ::CLGIBCall;
1468 default:
1469 return 0;
1470 }
1471 case SystemZII::CompareAndTrap:
1472 switch (Opcode) {
1473 case SystemZ::CR:
1474 return SystemZ::CRT;
1475 case SystemZ::CGR:
1476 return SystemZ::CGRT;
1477 case SystemZ::CHI:
1478 return SystemZ::CIT;
1479 case SystemZ::CGHI:
1480 return SystemZ::CGIT;
1481 case SystemZ::CLR:
1482 return SystemZ::CLRT;
1483 case SystemZ::CLGR:
1484 return SystemZ::CLGRT;
1485 case SystemZ::CLFI:
1486 return SystemZ::CLFIT;
1487 case SystemZ::CLGFI:
1488 return SystemZ::CLGIT;
1489 default:
1490 return 0;
1491 }
1492 }
1493 return 0;
1494 }
1495
loadImmediate(MachineBasicBlock & MBB,MachineBasicBlock::iterator MBBI,unsigned Reg,uint64_t Value) const1496 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
1497 MachineBasicBlock::iterator MBBI,
1498 unsigned Reg, uint64_t Value) const {
1499 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
1500 unsigned Opcode;
1501 if (isInt<16>(Value))
1502 Opcode = SystemZ::LGHI;
1503 else if (SystemZ::isImmLL(Value))
1504 Opcode = SystemZ::LLILL;
1505 else if (SystemZ::isImmLH(Value)) {
1506 Opcode = SystemZ::LLILH;
1507 Value >>= 16;
1508 } else {
1509 assert(isInt<32>(Value) && "Huge values not handled yet");
1510 Opcode = SystemZ::LGFI;
1511 }
1512 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);
1513 }
1514