Home
last modified time | relevance | path

Searched defs:SrcR (Results 1 – 21 of 21) sorted by relevance

/aosp_15_r20/external/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp1381 unsigned SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1403 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1466 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1549 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1653 unsigned SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
H A DHexagonGenInsert.cpp433 unsigned SrcR, InsR; member
447 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
637 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm()
839 unsigned SrcR = *I; in findRecordInsertForms() local
H A DRDFCopy.cpp36 RegisterRef SrcR = { Src.getReg(), Src.getSubReg() }; in interpretAsCopy() local
H A DHexagonRDFOpt.cpp98 auto mapRegs = [MI,&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in interpretAsCopy()
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/
H A DHexagonGenInsert.cpp470 unsigned SrcR, InsR; member
486 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
674 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm()
864 for (unsigned SrcR : AVs) { in findRecordInsertForms() local
H A DHexagonFrameLowering.cpp1722 Register SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1746 Register SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1809 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1896 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1985 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
H A DRDFCopy.cpp47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy() local
H A DHexagonRDFOpt.cpp113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonBitSimplify.cpp2245 unsigned SrcR = B0.RefI.Reg; in genBitSplit() local
H A DHexagonConstPropagation.cpp1943 RegisterSubReg SrcR(MI.getOperand(1)); in evaluate() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/
H A DHexagonFrameLowering.cpp1608 Register SrcR = MI->getOperand(1).getReg(); in expandCopy() local
1632 Register SrcR = MI->getOperand(2).getReg(); in expandStoreInt() local
1695 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVecPred() local
1782 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec2() local
1882 Register SrcR = MI->getOperand(2).getReg(); in expandStoreVec() local
H A DHexagonGenInsert.cpp471 unsigned SrcR, InsR; member
487 unsigned SrcR = P.IFR.SrcR, InsR = P.IFR.InsR; in operator <<() local
684 bool HexagonGenInsert::isValidInsertForm(unsigned DstR, unsigned SrcR, in isValidInsertForm()
881 unsigned SrcR = *I; in findRecordInsertForms() local
H A DRDFCopy.cpp47 RegisterRef SrcR = DFG.makeRegRef(Src.getReg(), Src.getSubReg()); in interpretAsCopy() local
H A DHexagonRDFOpt.cpp113 auto mapRegs = [&EM] (RegisterRef DstR, RegisterRef SrcR) -> void { in INITIALIZE_PASS_DEPENDENCY()
H A DHexagonBitSimplify.cpp2210 unsigned SrcR = B0.RefI.Reg; in genBitSplit() local
H A DHexagonConstPropagation.cpp1944 RegisterSubReg SrcR(MI.getOperand(1)); in evaluate() local
/aosp_15_r20/external/swiftshader/third_party/subzero/src/
H A DIceTargetLoweringMIPS32.cpp1812 Variable *SrcR; in legalizeMovFp() local
1843 auto *SrcR = llvm::cast<Variable>(Src); in legalizeMov() local
1933 auto *SrcR = llvm::cast<Variable>(Src); in legalizeMov() local
3038 Operand *SrcR; in lowerAssign() local
4886 auto *SrcR = legalizeToReg(Src); in lowerIntrinsic() local
4902 auto *SrcR = legalizeToReg(Src); in lowerIntrinsic() local
4979 auto *SrcR = legalizeToReg(Src); in lowerIntrinsic() local
5019 auto *SrcR = legalizeToReg(Src); in lowerIntrinsic() local
H A DIceTargetLoweringARM32.cpp1692 auto *SrcR = llvm::cast<Variable>(Src); in legalizeMov() local
/aosp_15_r20/external/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp388 const MachineOperand &SrcR = MI.getOperand(SrcR1 == DstR ? 1 : 3); in processInstructionForSLM() local
/aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp517 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; in processInstructionForSlowLEA() local
/aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/X86/
H A DX86FixupLEAs.cpp733 const MachineOperand &SrcR = SrcR1 == DstR ? Base : Index; in processInstructionForSlowLEA() local