| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 1183 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeRead2Pair() local
1322 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair() local
1371 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeSMemLoadImmPair() local
1421 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferLoadPair() local
1476 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeTBufferLoadPair() local
1540 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeTBufferStorePair() local
1590 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeFlatLoadPair() local
1638 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeFlatStorePair() local
1864 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferStorePair() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 982 const TargetRegisterClass *SuperRC = in mergeRead2Pair() local
1124 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeImagePair() local
1177 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeSBufferLoadImmPair() local
1228 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferLoadPair() local
1290 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeTBufferLoadPair() local
1362 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeTBufferStorePair() local
1524 const TargetRegisterClass *SuperRC = getTargetRegisterClass(CI, Paired); in mergeBufferStorePair() local
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| H A D | SIInstrInfo.cpp | 3864 const TargetRegisterClass *SuperRC, in buildExtractSubReg()
3897 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm()
3936 const TargetRegisterClass *SuperRC = RI.getLargestLegalSuperClass(RC, *MF); in isLegalRegOperand() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 331 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
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| H A D | HexagonCopyToCombine.cpp | 588 const TargetRegisterClass *SuperRC = nullptr; in combine() local
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| /aosp_15_r20/external/llvm/lib/Target/AMDGPU/ |
| H A D | SILoadStoreOptimizer.cpp | 229 const TargetRegisterClass *SuperRC in mergeRead2Pair() local
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| H A D | SILowerControlFlow.cpp | 604 const TargetRegisterClass *SuperRC = TRI->getPhysRegClass(VecReg); in computeIndirectRegAndOffset() local
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| H A D | SIInstrInfo.cpp | 1904 const TargetRegisterClass *SuperRC, in buildExtractSubReg()
1937 const TargetRegisterClass *SuperRC, in buildExtractSubRegOrImm()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/Target/Hexagon/ |
| H A D | HexagonRegisterInfo.cpp | 439 if (const TargetRegisterClass *SuperRC = *RC.getSuperClasses()) in getHexagonSubRegIndex() local
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| H A D | HexagonCopyToCombine.cpp | 583 const TargetRegisterClass *SuperRC = nullptr; in combine() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/lib/CodeGen/ |
| H A D | RegAllocGreedy.cpp | 1247 const MachineInstr *MI, Register Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints()
1341 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
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| H A D | AggressiveAntiDepBreaker.cpp | 615 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
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| /aosp_15_r20/external/llvm/lib/CodeGen/ |
| H A D | RegAllocGreedy.cpp | 1560 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints()
1599 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
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| H A D | TargetLoweringBase.cpp | 1277 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
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| H A D | AggressiveAntiDepBreaker.cpp | 611 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
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| /aosp_15_r20/external/swiftshader/third_party/llvm-10.0/llvm/lib/CodeGen/ |
| H A D | MachineCopyPropagation.cpp | 435 const TargetRegisterClass *SuperRC = UseDstRC; in isForwardableRegClassCopy() local
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| H A D | RegAllocGreedy.cpp | 2065 const MachineInstr *MI, unsigned Reg, const TargetRegisterClass *SuperRC, in getNumAllocatableRegsForConstraints()
2105 const TargetRegisterClass *SuperRC = in tryInstructionSplit() local
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| H A D | AggressiveAntiDepBreaker.cpp | 629 const TargetRegisterClass *SuperRC = in FindSuitableFreeRegisters() local
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| H A D | TargetLoweringBase.cpp | 1128 const TargetRegisterClass *SuperRC = TRI->getRegClass(i); in findRepresentativeClass() local
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| /aosp_15_r20/external/llvm/utils/TableGen/ |
| H A D | CodeGenRegisters.h | 365 CodeGenRegisterClass *SuperRC) { in addSuperRegClass()
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| /aosp_15_r20/external/swiftshader/third_party/llvm-16.0/llvm/include/llvm/CodeGen/ |
| H A D | TargetRegisterInfo.h | 644 getSubRegisterClass(const TargetRegisterClass *SuperRC, in getSubRegisterClass()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 657 getSubRegisterClass(const TargetRegisterClass *SuperRC, in getSubRegisterClass()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 684 getSubRegisterClass(const TargetRegisterClass *SuperRC, in getSubRegisterClass()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 659 getSubRegisterClass(const TargetRegisterClass *SuperRC, in getSubRegisterClass()
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| /aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/include/llvm/CodeGen/ |
| D | TargetRegisterInfo.h | 659 getSubRegisterClass(const TargetRegisterClass *SuperRC, in getSubRegisterClass()
|