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Searched defs:ctrlReg (Results 1 – 5 of 5) sorted by relevance

/XiangShan/src/main/scala/xiangshan/backend/fu/wrapper/
H A DDivUnit.scala31 val ctrlReg = RegEnable(ctrl, io.in.fire) constant
/XiangShan/src/main/scala/xiangshan/backend/fu/fpu/
H A DIntToFP.scala43 val ctrlReg = RegEnable(ctrl, regEnables(0)) constant
/XiangShan/src/main/scala/xiangshan/backend/fu/
H A DRadix2Divider.scala58 val ctrlReg = RegEnable(ctrl, newReq) constant
H A DSRT4Divider.scala437 val ctrlReg = RegEnable(ctrl, newReq) constant
/XiangShan/src/main/scala/xiangshan/cache/dcache/
H A DCtrlUnit.scala89 val ctrlReg = ctrlRegs.head constant