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/linux-6.14.4/Documentation/admin-guide/media/
Dimx7.rst41 virtual channel 0. This module is compliant to previous version of Samsung
48 sensor with a parallel interface or from MIPI CSI-2 virtual channel 0. It has
78 an output of 800x600, and BGGR 10 bit bayer format:
83 media-ctl -l "'ov2680 1-0036':0 -> 'imx7-mipi-csis.0':0[1]"
84 media-ctl -l "'imx7-mipi-csis.0':1 -> 'csi-mux':1[1]"
85 media-ctl -l "'csi-mux':2 -> 'csi':0[1]"
86 media-ctl -l "'csi':1 -> 'csi capture':0[1]"
89 media-ctl -V "'ov2680 1-0036':0 [fmt:SBGGR10_1X10/800x600 field:none]"
90 media-ctl -V "'csi-mux':1 [fmt:SBGGR10_1X10/800x600 field:none]"
91 media-ctl -V "'csi-mux':2 [fmt:SBGGR10_1X10/800x600 field:none]"
[all …]
/linux-6.14.4/drivers/video/fbdev/
Dmacmodes.h20 #define VMODE_NVRAM 0
29 #define VMODE_800_600_56 9 /* 800x600, 56Hz */
30 #define VMODE_800_600_60 10 /* 800x600, 60Hz */
31 #define VMODE_800_600_72 11 /* 800x600, 72Hz */
32 #define VMODE_800_600_75 12 /* 800x600, 75Hz */
48 #define CMODE_8 0 /* 8 bits/pixel */
68 #define NV_VMODE 0x140f
69 #define NV_CMODE 0x1410
Dcontrolfb.h97 * 3.9064MHz * 2**clock_params[2] * clock_params[1] / clock_params[0].
106 #define CTRLFB_OFF 16 /* position of pixel 0 in frame buffer */
113 int m[2]; /* 0: 2MB vram, 1: 4MB vram */
128 {{ 2, 2}}, /* 800x600, 56Hz */
129 {{ 2, 2}}, /* 800x600, 60Hz */
130 {{ 2, 2}}, /* 800x600, 72Hz */
131 {{ 2, 2}}, /* 800x600, 75Hz */
138 {{ 0, 1}}, /* 1280x960, 75Hz */
139 {{ 0, 1}}, /* 1280x1024, 75Hz */
141 {{ 0, 1}}, /* 1600x1024, 60Hz */
Dmacmodes.c32 #define DEFAULT_MODEDB_INDEX 0
38 0, FB_VMODE_NONINTERLACED
42 0, FB_VMODE_NONINTERLACED
46 0, FB_VMODE_NONINTERLACED
50 0, FB_VMODE_NONINTERLACED
52 /* 800x600, 56 Hz, Non-Interlaced (36.00 MHz dotclock) */
56 /* 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock) */
60 /* 800x600, 72 Hz, Non-Interlaced (50.00 MHz dotclock) */
64 /* 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock) */
70 0, FB_VMODE_NONINTERLACED
[all …]
/linux-6.14.4/Documentation/fb/
Dviafb.modes182 # 800x600, 60 Hz, Non-Interlaced (40.00 MHz dotclock)
199 mode "800x600-60"
204 # 800x600, 75 Hz, Non-Interlaced (49.50 MHz dotclock)
221 mode "800x600-75"
226 # 800x600, 85 Hz, Non-Interlaced (56.25 MHz dotclock)
243 mode "800x600-85"
248 # 800x600, 100 Hz, Non-Interlaced (67.50 MHz dotclock)
256 # 0 chars 7 lines
265 mode "800x600-100"
268 timings 14667 216 0 14 7 64 4 hsync high vsync high endmode
[all …]
Dviafb.rst22 720x576(60 Hz), 800x600(60, 75, 85, 100, 120 Hz),
41 #modprobe viafb viafb_mode=800x600 viafb_bpp=16 viafb_refresh=60
49 - 800x600
59 - 0 : expansion (default)
63 0 : LCD panel with LSB data format input (default)
67 - 0 : Resolution: 640x480, Channel: single, Dithering: Enable
68 - 1 : Resolution: 800x600, Channel: single, Dithering: Enable
84 - 17: Resolution: 1024x600, Channel: single, Dithering: Enable
89 - 0 : No 2D Hardware Acceleration
93 - 0 : viafb_SAMM_ON disable (default)
[all …]
/linux-6.14.4/drivers/video/fbdev/sis/
Doem310.h55 0x00,0x00,0x00, /* 800x600 */
56 0x0b,0x0b,0x0b, /* 1024x768 */
57 0x08,0x08,0x08, /* 1280x1024 */
58 0x00,0x00,0x00, /* 640x480 (unknown) */
59 0x00,0x00,0x00, /* 1024x600 (unknown) */
60 0x00,0x00,0x00, /* 1152x864 (unknown) */
61 0x08,0x08,0x08, /* 1280x960 (guessed) */
62 0x00,0x00,0x00, /* 1152x768 (unknown) */
63 0x08,0x08,0x08, /* 1400x1050 */
64 0x08,0x08,0x08, /* 1280x768 (guessed) */
[all …]
/linux-6.14.4/arch/arm/boot/dts/broadcom/
Dbcm63148.dtsi18 #size-cells = <0>;
20 B15_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
81 ranges = <0 0x80030000 0x8000>;
87 reg = <0x1000 0x1000>,
88 <0x2000 0x2000>,
89 <0x4000 0x2000>,
[all …]
Dbcm63138.dtsi23 #size-cells = <0>;
25 cpu@0 {
29 reg = <0>;
46 #clock-cells = <0>;
54 #clock-cells = <0>;
63 #clock-cells = <0>;
72 #clock-cells = <0>;
80 ranges = <0 0x80000000 0x784000>;
86 reg = <0x1d000 0x1000>;
92 interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>;
[all …]
Dbcm6878.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
62 #clock-cells = <0>;
68 #clock-cells = <0>;
76 #clock-cells = <0>;
90 ranges = <0 0x81000000 0x8000>;
96 reg = <0x1000 0x1000>,
97 <0x2000 0x2000>,
[all …]
Dbcm6855.dtsi18 #size-cells = <0>;
20 CA7_0: cpu@0 {
23 reg = <0x0>;
31 reg = <0x1>;
39 reg = <0x2>;
71 #clock-cells = <0>;
77 #clock-cells = <0>;
85 #clock-cells = <0>;
99 ranges = <0 0x81000000 0x8000>;
106 reg = <0x1000 0x1000>,
[all …]
/linux-6.14.4/drivers/video/fbdev/geode/
Dlxfb_core.c41 FB_VMODE_NONINTERLACED, 0 },
45 FB_VMODE_NONINTERLACED, 0 },
48 0, FB_VMODE_NONINTERLACED, 0 },
52 FB_VMODE_NONINTERLACED, 0 },
56 FB_VMODE_NONINTERLACED, 0 },
60 FB_VMODE_NONINTERLACED, 0 },
63 0, FB_VMODE_NONINTERLACED, 0 },
66 0, FB_VMODE_NONINTERLACED, 0 },
70 FB_VMODE_NONINTERLACED, 0 },
71 /* 800x600-56 */
[all …]
/linux-6.14.4/arch/xtensa/platforms/xtfpga/include/platform/
Dhardware.h37 #define DUART16552_PADDR (XCHAL_KIO_PADDR + 0x0D050020)
40 #define XTFPGA_FPGAREGS_VADDR IOADDR(0x0D020000)
42 #define XTFPGA_CLKFRQ_VADDR (XTFPGA_FPGAREGS_VADDR + 0x04)
44 #define DIP_SWITCHES_VADDR (XTFPGA_FPGAREGS_VADDR + 0x0C)
45 /* Software reset (write 0xdead): */
46 #define XTFPGA_SWRST_VADDR (XTFPGA_FPGAREGS_VADDR + 0x10)
50 #define OETH_REGS_PADDR (XCHAL_KIO_PADDR + 0x0D030000)
51 #define OETH_REGS_SIZE 0x1000
52 #define OETH_SRAMBUFF_PADDR (XCHAL_KIO_PADDR + 0x0D800000)
55 #define OETH_SRAMBUFF_SIZE (5 * 0x600 + 5 * 0x600)
[all …]
/linux-6.14.4/include/dt-bindings/clock/
Dlpc18xx-ccu.h13 #define CLK_APB3_BUS 0x100
14 #define CLK_APB3_I2C1 0x108
15 #define CLK_APB3_DAC 0x110
16 #define CLK_APB3_ADC0 0x118
17 #define CLK_APB3_ADC1 0x120
18 #define CLK_APB3_CAN0 0x128
19 #define CLK_APB1_BUS 0x200
20 #define CLK_APB1_MOTOCON_PWM 0x208
21 #define CLK_APB1_I2C0 0x210
22 #define CLK_APB1_I2S 0x218
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Datmel-hsmci.txt26 reg = <0xf0008000 0x600>;
29 #size-cells = <0>;
49 slot@0 {
50 reg = <0>;
52 cd-gpios = <&pioD 15 0>
59 reg = <0xf0008000 0x600>;
62 #size-cells = <0>;
63 slot@0 {
64 reg = <0>;
66 cd-gpios = <&pioD 15 0>
/linux-6.14.4/arch/arm/boot/dts/microchip/
Dsam9x7.dtsi36 #size-cells = <0>;
38 cpu@0 {
40 reg = <0>;
48 #clock-cells = <0>;
53 #clock-cells = <0>;
59 reg = <0x300000 0x10000>;
60 ranges = <0 0x300000 0x10000>;
73 reg = <0x80000000 0x300>;
74 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>;
84 reg = <0x90000000 0x300>;
[all …]
Dsam9x60.dtsi37 #size-cells = <0>;
39 cpu@0 {
42 reg = <0>;
48 reg = <0x20000000 0x10000000>;
54 #clock-cells = <0>;
59 #clock-cells = <0>;
65 reg = <0x00300000 0x100000>;
68 ranges = <0 0x00300000 0x100000>;
79 #size-cells = <0>;
81 reg = <0x00500000 0x100000
[all …]
/linux-6.14.4/arch/arm64/boot/dts/qcom/
Dmsm8998.dtsi16 qcom,msm-id = <292 0x0>;
26 reg = <0x0 0x80000000 0x0 0x0>;
35 reg = <0x0 0x85800000 0x0 0x600000>;
40 reg = <0x0 0x85e00000 0x0 0x100000>;
45 reg = <0x0 0x86000000 0x0 0x200000>;
50 reg = <0x0 0x86200000 0x0 0x2d00000>;
56 reg = <0x0 0x88f00000 0x0 0x200000>;
64 reg = <0x0 0x8ab00000 0x0 0x700000>;
69 reg = <0x0 0x8b200000 0x0 0x1a00000>;
74 reg = <0x0 0x8cc00000 0x0 0x7000000>;
[all …]
/linux-6.14.4/drivers/video/fbdev/via/
Dlcd.h11 #define VT1631_DEVICE_ID_REG 0x02
12 #define VT1631_DEVICE_ID 0x92
14 #define VT3271_DEVICE_ID_REG 0x02
15 #define VT3271_DEVICE_ID 0x71
19 #define LCD_PANEL_ID0_640X480 0x00
20 /* Resolution: 800x600, Channel: single, Dithering: Enable */
21 #define LCD_PANEL_ID1_800X600 0x01
23 #define LCD_PANEL_ID2_1024X768 0x02
25 #define LCD_PANEL_ID3_1280X768 0x03
27 #define LCD_PANEL_ID4_1280X1024 0x04
[all …]
/linux-6.14.4/drivers/gpu/drm/loongson/
Dlsdc_pixpll.c21 /* Byte 0 ~ Byte 3 */
22 unsigned div_out : 7; /* 6 : 0 Output clock divider */
85 {51200, 1024, 600, 60, 25, 64, 5}, /* 1024x600@60Hz */
88 {49500, 800, 600, 75, 40, 99, 5}, /* 800x600@75Hz */
89 {50000, 800, 600, 72, 44, 88, 4}, /* 800x600@72Hz */
90 {40000, 800, 600, 60, 30, 36, 3}, /* 800x600@60Hz */
91 {36000, 800, 600, 56, 50, 72, 4}, /* 800x600@56Hz */
147 * Return 0 if success, return -1 if not found.
157 for (i = 0; i < num; ++i) { in lsdc_pixpll_find()
165 return 0; in lsdc_pixpll_find()
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/pinctrl/
Dfsl,imx27-pinctrl.txt12 PIN is an integer between 0 and 0xbf. imx27 has 6 ports with 32 configurable
14 number on the specific port (between 0 and 31).
21 0 - Primary function
28 0 - Input
37 0 - A_IN
46 0 - GPIO_IN
52 CONFIG can be 0 or 1, meaning Pullup disable/enable.
64 reg = <0x10015000 0x600>;
78 0x8c 0x004 0x0 /* UART1_TXD__UART1_TXD */
79 0x8d 0x000 0x0 /* UART1_RXD__UART1_RXD */
[all …]
/linux-6.14.4/drivers/video/fbdev/i810/
Di810_dvt.c21 { 25000, 0x0013, 0x0003, 0x40, 0x5F, 0x4F, 0x50, 0x82, 0x51, 0x9D,
22 0x0B, 0x10, 0x40, 0xE9, 0x0B, 0xDF, 0x50, 0xE7, 0x04, 0x02,
23 0x01, 0x01, 0x01, 0x00, 0x01, 0x22002000, 0x22004000, 0x22006000,
24 0x22002000, 0x22004000, 0x22006000, 0xC0 },
27 { 28000, 0x0053, 0x0010, 0x40, 0x61, 0x4F, 0x4F, 0x85, 0x52, 0x9A,
28 0xF2, 0x10, 0x40, 0xE0, 0x03, 0xDF, 0x50, 0xDF, 0xF3, 0x01,
29 0x01, 0x01, 0x01, 0x00, 0x01, 0x22002000, 0x22004000, 0x22005000,
30 0x22002000, 0x22004000, 0x22005000, 0xC0 },
33 { 31000, 0x0013, 0x0002, 0x40, 0x63, 0x4F, 0x4F, 0x87, 0x52, 0x97,
34 0x06, 0x0F, 0x40, 0xE8, 0x0B, 0xDF, 0x50, 0xDF, 0x07, 0x02,
[all …]
/linux-6.14.4/arch/arm64/boot/dts/broadcom/bcmbca/
Dbcm6856.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
81 ranges = <0x0 0x0 0x81000000 0x8000>;
87 reg = <0x1000 0x1000>, /* GICD */
88 <0x2000 0x2000>, /* GICC */
89 <0x4000 0x2000>, /* GICH */
[all …]
Dbcm63146.dtsi18 #size-cells = <0>;
20 B53_0: cpu@0 {
23 reg = <0x0 0x0>;
31 reg = <0x0 0x1>;
61 #clock-cells = <0>;
67 #clock-cells = <0>;
75 #clock-cells = <0>;
89 ranges = <0x0 0x0 0x81000000 0x8000>;
95 reg = <0x1000 0x1000>,
96 <0x2000 0x2000>,
[all …]
/linux-6.14.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu_vcn.h38 #define AMDGPU_VCN_HARVEST_VCN0 (1 << 0)
41 #define VCN_DEC_KMD_CMD 0x80000000
42 #define VCN_DEC_CMD_FENCE 0x00000000
43 #define VCN_DEC_CMD_TRAP 0x00000001
44 #define VCN_DEC_CMD_WRITE_REG 0x00000004
45 #define VCN_DEC_CMD_REG_READ_COND_WAIT 0x00000006
46 #define VCN_DEC_CMD_PACKET_START 0x0000000a
47 #define VCN_DEC_CMD_PACKET_END 0x0000000b
49 #define VCN_DEC_SW_CMD_NO_OP 0x00000000
50 #define VCN_DEC_SW_CMD_END 0x00000001
[all …]

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