1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * sam9x7.dtsi - Device Tree Include file for Microchip SAM9X7 SoC family 4 * 5 * Copyright (C) 2023 Microchip Technology Inc. and its subsidiaries 6 * 7 * Author: Varshini Rajendran <[email protected]> 8 */ 9 10#include <dt-bindings/clock/at91.h> 11#include <dt-bindings/dma/at91.h> 12#include <dt-bindings/gpio/gpio.h> 13#include <dt-bindings/interrupt-controller/arm-gic.h> 14#include <dt-bindings/interrupt-controller/irq.h> 15#include <dt-bindings/mfd/at91-usart.h> 16#include <dt-bindings/mfd/atmel-flexcom.h> 17#include <dt-bindings/pinctrl/at91.h> 18 19/ { 20 model = "Microchip SAM9X7 SoC"; 21 compatible = "microchip,sam9x7"; 22 #address-cells = <1>; 23 #size-cells = <1>; 24 interrupt-parent = <&aic>; 25 26 aliases { 27 serial0 = &dbgu; 28 gpio0 = &pioA; 29 gpio1 = &pioB; 30 gpio2 = &pioC; 31 gpio3 = &pioD; 32 }; 33 34 cpus { 35 #address-cells = <1>; 36 #size-cells = <0>; 37 38 cpu@0 { 39 compatible = "arm,arm926ej-s"; 40 reg = <0>; 41 device_type = "cpu"; 42 }; 43 }; 44 45 clocks { 46 slow_xtal: clock-slowxtal { 47 compatible = "fixed-clock"; 48 #clock-cells = <0>; 49 }; 50 51 main_xtal: clock-mainxtal { 52 compatible = "fixed-clock"; 53 #clock-cells = <0>; 54 }; 55 }; 56 57 sram: sram@300000 { 58 compatible = "mmio-sram"; 59 reg = <0x300000 0x10000>; 60 ranges = <0 0x300000 0x10000>; 61 #address-cells = <1>; 62 #size-cells = <1>; 63 }; 64 65 ahb { 66 compatible = "simple-bus"; 67 ranges; 68 #address-cells = <1>; 69 #size-cells = <1>; 70 71 sdmmc0: mmc@80000000 { 72 compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; 73 reg = <0x80000000 0x300>; 74 interrupts = <12 IRQ_TYPE_LEVEL_HIGH 0>; 75 clocks = <&pmc PMC_TYPE_PERIPHERAL 12>, <&pmc PMC_TYPE_GCK 12>; 76 clock-names = "hclock", "multclk"; 77 assigned-clocks = <&pmc PMC_TYPE_GCK 12>; 78 assigned-clock-rates = <100000000>; 79 status = "disabled"; 80 }; 81 82 sdmmc1: mmc@90000000 { 83 compatible = "microchip,sam9x7-sdhci", "microchip,sam9x60-sdhci"; 84 reg = <0x90000000 0x300>; 85 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0>; 86 clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_GCK 26>; 87 clock-names = "hclock", "multclk"; 88 assigned-clocks = <&pmc PMC_TYPE_GCK 26>; 89 assigned-clock-rates = <100000000>; 90 status = "disabled"; 91 }; 92 }; 93 94 apb { 95 compatible = "simple-bus"; 96 ranges; 97 #address-cells = <1>; 98 #size-cells = <1>; 99 100 flx4: flexcom@f0000000 { 101 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 102 reg = <0xf0000000 0x200>; 103 ranges = <0x0 0xf0000000 0x800>; 104 #address-cells = <1>; 105 #size-cells = <1>; 106 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 107 status = "disabled"; 108 109 uart4: serial@200 { 110 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 111 reg = <0x200 0x200>; 112 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 113 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 114 clock-names = "usart"; 115 dmas = <&dma0 116 (AT91_XDMAC_DT_MEM_IF(0) | 117 AT91_XDMAC_DT_PER_IF(1) | 118 AT91_XDMAC_DT_PERID(8))>, 119 <&dma0 120 (AT91_XDMAC_DT_MEM_IF(0) | 121 AT91_XDMAC_DT_PER_IF(1) | 122 AT91_XDMAC_DT_PERID(9))>; 123 dma-names = "tx", "rx"; 124 atmel,use-dma-rx; 125 atmel,use-dma-tx; 126 atmel,fifo-size = <16>; 127 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 128 status = "disabled"; 129 }; 130 131 spi4: spi@400 { 132 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 133 reg = <0x400 0x200>; 134 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 135 #address-cells = <1>; 136 #size-cells = <0>; 137 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 138 clock-names = "spi_clk"; 139 dmas = <&dma0 140 (AT91_XDMAC_DT_MEM_IF(0) | 141 AT91_XDMAC_DT_PER_IF(1) | 142 AT91_XDMAC_DT_PERID(8))>, 143 <&dma0 144 (AT91_XDMAC_DT_MEM_IF(0) | 145 AT91_XDMAC_DT_PER_IF(1) | 146 AT91_XDMAC_DT_PERID(9))>; 147 dma-names = "tx", "rx"; 148 atmel,fifo-size = <16>; 149 status = "disabled"; 150 }; 151 152 i2c4: i2c@600 { 153 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 154 reg = <0x600 0x200>; 155 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 7>; 156 #address-cells = <1>; 157 #size-cells = <0>; 158 clocks = <&pmc PMC_TYPE_PERIPHERAL 13>; 159 dmas = <&dma0 160 (AT91_XDMAC_DT_MEM_IF(0) | 161 AT91_XDMAC_DT_PER_IF(1) | 162 AT91_XDMAC_DT_PERID(8))>, 163 <&dma0 164 (AT91_XDMAC_DT_MEM_IF(0) | 165 AT91_XDMAC_DT_PER_IF(1) | 166 AT91_XDMAC_DT_PERID(9))>; 167 dma-names = "tx", "rx"; 168 atmel,fifo-size = <16>; 169 status = "disabled"; 170 }; 171 }; 172 173 flx5: flexcom@f0004000 { 174 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 175 reg = <0xf0004000 0x200>; 176 ranges = <0x0 0xf0004000 0x800>; 177 #address-cells = <1>; 178 #size-cells = <1>; 179 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 180 status = "disabled"; 181 182 uart5: serial@200 { 183 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 184 reg = <0x200 0x200>; 185 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 186 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 187 clock-names = "usart"; 188 dmas = <&dma0 189 (AT91_XDMAC_DT_MEM_IF(0) | 190 AT91_XDMAC_DT_PER_IF(1) | 191 AT91_XDMAC_DT_PERID(10))>, 192 <&dma0 193 (AT91_XDMAC_DT_MEM_IF(0) | 194 AT91_XDMAC_DT_PER_IF(1) | 195 AT91_XDMAC_DT_PERID(11))>; 196 dma-names = "tx", "rx"; 197 atmel,use-dma-rx; 198 atmel,use-dma-tx; 199 atmel,fifo-size = <16>; 200 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 201 status = "disabled"; 202 }; 203 204 spi5: spi@400 { 205 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 206 reg = <0x400 0x200>; 207 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 208 #address-cells = <1>; 209 #size-cells = <0>; 210 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 211 clock-names = "spi_clk"; 212 dmas = <&dma0 213 (AT91_XDMAC_DT_MEM_IF(0) | 214 AT91_XDMAC_DT_PER_IF(1) | 215 AT91_XDMAC_DT_PERID(10))>, 216 <&dma0 217 (AT91_XDMAC_DT_MEM_IF(0) | 218 AT91_XDMAC_DT_PER_IF(1) | 219 AT91_XDMAC_DT_PERID(11))>; 220 dma-names = "tx", "rx"; 221 atmel,fifo-size = <16>; 222 status = "disabled"; 223 }; 224 225 i2c5: i2c@600 { 226 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 227 reg = <0x600 0x200>; 228 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 7>; 229 #address-cells = <1>; 230 #size-cells = <0>; 231 clocks = <&pmc PMC_TYPE_PERIPHERAL 14>; 232 dmas = <&dma0 233 (AT91_XDMAC_DT_MEM_IF(0) | 234 AT91_XDMAC_DT_PER_IF(1) | 235 AT91_XDMAC_DT_PERID(10))>, 236 <&dma0 237 (AT91_XDMAC_DT_MEM_IF(0) | 238 AT91_XDMAC_DT_PER_IF(1) | 239 AT91_XDMAC_DT_PERID(11))>; 240 dma-names = "tx", "rx"; 241 atmel,fifo-size = <16>; 242 status = "disabled"; 243 }; 244 }; 245 246 dma0: dma-controller@f0008000 { 247 compatible = "microchip,sam9x7-dma", "atmel,sama5d4-dma"; 248 reg = <0xf0008000 0x1000>; 249 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 0>; 250 #dma-cells = <1>; 251 clocks = <&pmc PMC_TYPE_PERIPHERAL 20>; 252 clock-names = "dma_clk"; 253 status = "disabled"; 254 }; 255 256 ssc: ssc@f0010000 { 257 compatible = "microchip,sam9x7-ssc", "atmel,at91sam9g45-ssc"; 258 reg = <0xf0010000 0x4000>; 259 interrupts = <28 IRQ_TYPE_LEVEL_HIGH 5>; 260 clocks = <&pmc PMC_TYPE_PERIPHERAL 28>; 261 clock-names = "pclk"; 262 dmas = <&dma0 263 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 264 AT91_XDMAC_DT_PERID(38))>, 265 <&dma0 266 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 267 AT91_XDMAC_DT_PERID(39))>; 268 dma-names = "tx", "rx"; 269 status = "disabled"; 270 }; 271 272 i2s: i2s@f001c000 { 273 compatible = "microchip,sam9x7-i2smcc", "microchip,sam9x60-i2smcc"; 274 reg = <0xf001c000 0x100>; 275 interrupts = <34 IRQ_TYPE_LEVEL_HIGH 7>; 276 clocks = <&pmc PMC_TYPE_PERIPHERAL 34>, <&pmc PMC_TYPE_GCK 34>; 277 clock-names = "pclk", "gclk"; 278 dmas = <&dma0 279 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 280 AT91_XDMAC_DT_PERID(36))>, 281 <&dma0 282 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 283 AT91_XDMAC_DT_PERID(37))>; 284 dma-names = "tx", "rx"; 285 status = "disabled"; 286 }; 287 288 flx11: flexcom@f0020000 { 289 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 290 reg = <0xf0020000 0x200>; 291 ranges = <0x0 0xf0020000 0x800>; 292 #address-cells = <1>; 293 #size-cells = <1>; 294 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 295 status = "disabled"; 296 297 uart11: serial@200 { 298 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 299 reg = <0x200 0x200>; 300 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 301 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 302 clock-names = "usart"; 303 dmas = <&dma0 304 (AT91_XDMAC_DT_MEM_IF(0) | 305 AT91_XDMAC_DT_PER_IF(1) | 306 AT91_XDMAC_DT_PERID(22))>, 307 <&dma0 308 (AT91_XDMAC_DT_MEM_IF(0) | 309 AT91_XDMAC_DT_PER_IF(1) | 310 AT91_XDMAC_DT_PERID(23))>; 311 dma-names = "tx", "rx"; 312 atmel,use-dma-rx; 313 atmel,use-dma-tx; 314 atmel,fifo-size = <16>; 315 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 316 status = "disabled"; 317 }; 318 319 i2c11: i2c@600 { 320 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 321 reg = <0x600 0x200>; 322 interrupts = <32 IRQ_TYPE_LEVEL_HIGH 7>; 323 #address-cells = <1>; 324 #size-cells = <0>; 325 clocks = <&pmc PMC_TYPE_PERIPHERAL 32>; 326 dmas = <&dma0 327 (AT91_XDMAC_DT_MEM_IF(0) | 328 AT91_XDMAC_DT_PER_IF(1) | 329 AT91_XDMAC_DT_PERID(22))>, 330 <&dma0 331 (AT91_XDMAC_DT_MEM_IF(0) | 332 AT91_XDMAC_DT_PER_IF(1) | 333 AT91_XDMAC_DT_PERID(23))>; 334 dma-names = "tx", "rx"; 335 atmel,fifo-size = <16>; 336 status = "disabled"; 337 }; 338 }; 339 340 flx12: flexcom@f0024000 { 341 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 342 reg = <0xf0024000 0x200>; 343 ranges = <0x0 0xf0024000 0x800>; 344 #address-cells = <1>; 345 #size-cells = <1>; 346 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 347 status = "disabled"; 348 349 uart12: serial@200 { 350 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 351 reg = <0x200 0x200>; 352 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 353 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 354 clock-names = "usart"; 355 dmas = <&dma0 356 (AT91_XDMAC_DT_MEM_IF(0) | 357 AT91_XDMAC_DT_PER_IF(1) | 358 AT91_XDMAC_DT_PERID(24))>, 359 <&dma0 360 (AT91_XDMAC_DT_MEM_IF(0) | 361 AT91_XDMAC_DT_PER_IF(1) | 362 AT91_XDMAC_DT_PERID(25))>; 363 dma-names = "tx", "rx"; 364 atmel,use-dma-rx; 365 atmel,use-dma-tx; 366 atmel,fifo-size = <16>; 367 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 368 status = "disabled"; 369 }; 370 371 i2c12: i2c@600 { 372 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 373 reg = <0x600 0x200>; 374 interrupts = <33 IRQ_TYPE_LEVEL_HIGH 7>; 375 #address-cells = <1>; 376 #size-cells = <0>; 377 clocks = <&pmc PMC_TYPE_PERIPHERAL 33>; 378 dmas = <&dma0 379 (AT91_XDMAC_DT_MEM_IF(0) | 380 AT91_XDMAC_DT_PER_IF(1) | 381 AT91_XDMAC_DT_PERID(24))>, 382 <&dma0 383 (AT91_XDMAC_DT_MEM_IF(0) | 384 AT91_XDMAC_DT_PER_IF(1) | 385 AT91_XDMAC_DT_PERID(25))>; 386 dma-names = "tx", "rx"; 387 atmel,fifo-size = <16>; 388 status = "disabled"; 389 }; 390 }; 391 392 pit64b0: timer@f0028000 { 393 compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; 394 reg = <0xf0028000 0x100>; 395 interrupts = <37 IRQ_TYPE_LEVEL_HIGH 7>; 396 clocks = <&pmc PMC_TYPE_PERIPHERAL 37>, <&pmc PMC_TYPE_GCK 37>; 397 clock-names = "pclk", "gclk"; 398 }; 399 400 sha: crypto@f002c000 { 401 compatible = "microchip,sam9x7-sha", "atmel,at91sam9g46-sha"; 402 reg = <0xf002c000 0x100>; 403 interrupts = <41 IRQ_TYPE_LEVEL_HIGH 0>; 404 clocks = <&pmc PMC_TYPE_PERIPHERAL 41>; 405 clock-names = "sha_clk"; 406 dmas = <&dma0 407 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 408 AT91_XDMAC_DT_PERID(34))>; 409 dma-names = "tx"; 410 }; 411 412 trng: rng@f0030000 { 413 compatible = "microchip,sam9x7-trng", "microchip,sam9x60-trng"; 414 reg = <0xf0030000 0x100>; 415 interrupts = <38 IRQ_TYPE_LEVEL_HIGH 0>; 416 clocks = <&pmc PMC_TYPE_PERIPHERAL 38>; 417 status = "disabled"; 418 }; 419 420 aes: crypto@f0034000 { 421 compatible = "microchip,sam9x7-aes", "atmel,at91sam9g46-aes"; 422 reg = <0xf0034000 0x100>; 423 interrupts = <39 IRQ_TYPE_LEVEL_HIGH 0>; 424 clocks = <&pmc PMC_TYPE_PERIPHERAL 39>; 425 clock-names = "aes_clk"; 426 dmas = <&dma0 427 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 428 AT91_XDMAC_DT_PERID(32))>, 429 <&dma0 430 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 431 AT91_XDMAC_DT_PERID(33))>; 432 dma-names = "tx", "rx"; 433 }; 434 435 tdes: crypto@f0038000 { 436 compatible = "microchip,sam9x7-tdes", "atmel,at91sam9g46-tdes"; 437 reg = <0xf0038000 0x100>; 438 interrupts = <40 IRQ_TYPE_LEVEL_HIGH 0>; 439 clocks = <&pmc PMC_TYPE_PERIPHERAL 40>; 440 clock-names = "tdes_clk"; 441 dmas = <&dma0 442 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 443 AT91_XDMAC_DT_PERID(31))>, 444 <&dma0 445 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 446 AT91_XDMAC_DT_PERID(30))>; 447 dma-names = "tx", "rx"; 448 }; 449 450 classd: sound@f003c000 { 451 compatible = "microchip,sam9x7-classd", "atmel,sama5d2-classd"; 452 reg = <0xf003c000 0x100>; 453 interrupts = <42 IRQ_TYPE_LEVEL_HIGH 7>; 454 clocks = <&pmc PMC_TYPE_PERIPHERAL 42>, <&pmc PMC_TYPE_GCK 42>; 455 clock-names = "pclk", "gclk"; 456 dmas = <&dma0 457 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 458 AT91_XDMAC_DT_PERID(35))>; 459 dma-names = "tx"; 460 status = "disabled"; 461 }; 462 463 pit64b1: timer@f0040000 { 464 compatible = "microchip,sam9x7-pit64b", "microchip,sam9x60-pit64b"; 465 reg = <0xf0040000 0x100>; 466 interrupts = <58 IRQ_TYPE_LEVEL_HIGH 7>; 467 clocks = <&pmc PMC_TYPE_PERIPHERAL 58>, <&pmc PMC_TYPE_GCK 58>; 468 clock-names = "pclk", "gclk"; 469 }; 470 471 can0: can@f8000000 { 472 compatible = "bosch,m_can"; 473 reg = <0xf8000000 0x100>, <0x300000 0x7800>; 474 reg-names = "m_can", "message_ram"; 475 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 0>, 476 <68 IRQ_TYPE_LEVEL_HIGH 0>; 477 interrupt-names = "int0", "int1"; 478 clocks = <&pmc PMC_TYPE_PERIPHERAL 29>, <&pmc PMC_TYPE_GCK 29>; 479 clock-names = "hclk", "cclk"; 480 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 29>; 481 assigned-clock-rates = <480000000>, <40000000>; 482 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 483 bosch,mram-cfg = <0x3400 0 0 64 0 0 32 32>; 484 status = "disabled"; 485 }; 486 487 can1: can@f8004000 { 488 compatible = "bosch,m_can"; 489 reg = <0xf8004000 0x100>, <0x300000 0xbc00>; 490 reg-names = "m_can", "message_ram"; 491 interrupts = <30 IRQ_TYPE_LEVEL_HIGH 0>, 492 <69 IRQ_TYPE_LEVEL_HIGH 0>; 493 interrupt-names = "int0", "int1"; 494 clocks = <&pmc PMC_TYPE_PERIPHERAL 30>, <&pmc PMC_TYPE_GCK 30>; 495 clock-names = "hclk", "cclk"; 496 assigned-clocks = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_GCK 30>; 497 assigned-clock-rates = <480000000>, <40000000>; 498 assigned-clock-parents = <&pmc PMC_TYPE_CORE PMC_UTMI>, <&pmc PMC_TYPE_CORE PMC_UTMI>; 499 bosch,mram-cfg = <0x7800 0 0 64 0 0 32 32>; 500 status = "disabled"; 501 }; 502 503 tcb: timer@f8008000 { 504 compatible = "microchip,sam9x7-tcb","atmel,sama5d2-tcb", "simple-mfd", "syscon"; 505 reg = <0xf8008000 0x100>; 506 #address-cells = <1>; 507 #size-cells = <0>; 508 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0>; 509 clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_GCK 17>, <&clk32k 0>; 510 clock-names = "t0_clk", "gclk", "slow_clk"; 511 }; 512 513 flx6: flexcom@f8010000 { 514 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 515 reg = <0xf8010000 0x200>; 516 ranges = <0x0 0xf8010000 0x800>; 517 #address-cells = <1>; 518 #size-cells = <1>; 519 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 520 status = "disabled"; 521 522 uart6: serial@200 { 523 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 524 reg = <0x200 0x200>; 525 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 526 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 527 clock-names = "usart"; 528 dmas = <&dma0 529 (AT91_XDMAC_DT_MEM_IF(0) | 530 AT91_XDMAC_DT_PER_IF(1) | 531 AT91_XDMAC_DT_PERID(12))>, 532 <&dma0 533 (AT91_XDMAC_DT_MEM_IF(0) | 534 AT91_XDMAC_DT_PER_IF(1) | 535 AT91_XDMAC_DT_PERID(13))>; 536 dma-names = "tx", "rx"; 537 atmel,use-dma-rx; 538 atmel,use-dma-tx; 539 atmel,fifo-size = <16>; 540 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 541 status = "disabled"; 542 }; 543 544 i2c6: i2c@600 { 545 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 546 reg = <0x600 0x200>; 547 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 7>; 548 #address-cells = <1>; 549 #size-cells = <0>; 550 clocks = <&pmc PMC_TYPE_PERIPHERAL 9>; 551 dmas = <&dma0 552 (AT91_XDMAC_DT_MEM_IF(0) | 553 AT91_XDMAC_DT_PER_IF(1) | 554 AT91_XDMAC_DT_PERID(12))>, 555 <&dma0 556 (AT91_XDMAC_DT_MEM_IF(0) | 557 AT91_XDMAC_DT_PER_IF(1) | 558 AT91_XDMAC_DT_PERID(13))>; 559 dma-names = "tx", "rx"; 560 atmel,fifo-size = <16>; 561 status = "disabled"; 562 }; 563 }; 564 565 flx7: flexcom@f8014000 { 566 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 567 reg = <0xf8014000 0x200>; 568 ranges = <0x0 0xf8014000 0x800>; 569 #address-cells = <1>; 570 #size-cells = <1>; 571 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 572 status = "disabled"; 573 574 uart7: serial@200 { 575 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 576 reg = <0x200 0x200>; 577 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 578 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 579 clock-names = "usart"; 580 dmas = <&dma0 581 (AT91_XDMAC_DT_MEM_IF(0) | 582 AT91_XDMAC_DT_PER_IF(1) | 583 AT91_XDMAC_DT_PERID(14))>, 584 <&dma0 585 (AT91_XDMAC_DT_MEM_IF(0) | 586 AT91_XDMAC_DT_PER_IF(1) | 587 AT91_XDMAC_DT_PERID(15))>; 588 dma-names = "tx", "rx"; 589 atmel,use-dma-rx; 590 atmel,use-dma-tx; 591 atmel,fifo-size = <16>; 592 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 593 status = "disabled"; 594 }; 595 596 i2c7: i2c@600 { 597 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 598 reg = <0x600 0x200>; 599 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 7>; 600 #address-cells = <1>; 601 #size-cells = <0>; 602 clocks = <&pmc PMC_TYPE_PERIPHERAL 10>; 603 dmas = <&dma0 604 (AT91_XDMAC_DT_MEM_IF(0) | 605 AT91_XDMAC_DT_PER_IF(1) | 606 AT91_XDMAC_DT_PERID(14))>, 607 <&dma0 608 (AT91_XDMAC_DT_MEM_IF(0) | 609 AT91_XDMAC_DT_PER_IF(1) | 610 AT91_XDMAC_DT_PERID(15))>; 611 dma-names = "tx", "rx"; 612 atmel,fifo-size = <16>; 613 status = "disabled"; 614 }; 615 }; 616 617 flx8: flexcom@f8018000 { 618 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 619 reg = <0xf8018000 0x200>; 620 ranges = <0x0 0xf8018000 0x800>; 621 #address-cells = <1>; 622 #size-cells = <1>; 623 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 624 status = "disabled"; 625 626 uart8: serial@200 { 627 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 628 reg = <0x200 0x200>; 629 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 630 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 631 clock-names = "usart"; 632 dmas = <&dma0 633 (AT91_XDMAC_DT_MEM_IF(0) | 634 AT91_XDMAC_DT_PER_IF(1) | 635 AT91_XDMAC_DT_PERID(16))>, 636 <&dma0 637 (AT91_XDMAC_DT_MEM_IF(0) | 638 AT91_XDMAC_DT_PER_IF(1) | 639 AT91_XDMAC_DT_PERID(17))>; 640 dma-names = "tx", "rx"; 641 atmel,use-dma-rx; 642 atmel,use-dma-tx; 643 atmel,fifo-size = <16>; 644 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 645 status = "disabled"; 646 }; 647 648 i2c8: i2c@600 { 649 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 650 reg = <0x600 0x200>; 651 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 7>; 652 #address-cells = <1>; 653 #size-cells = <0>; 654 clocks = <&pmc PMC_TYPE_PERIPHERAL 11>; 655 dmas = <&dma0 656 (AT91_XDMAC_DT_MEM_IF(0) | 657 AT91_XDMAC_DT_PER_IF(1) | 658 AT91_XDMAC_DT_PERID(16))>, 659 <&dma0 660 (AT91_XDMAC_DT_MEM_IF(0) | 661 AT91_XDMAC_DT_PER_IF(1) | 662 AT91_XDMAC_DT_PERID(17))>; 663 dma-names = "tx", "rx"; 664 atmel,fifo-size = <16>; 665 status = "disabled"; 666 }; 667 }; 668 669 flx0: flexcom@f801c000 { 670 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 671 reg = <0xf801c000 0x200>; 672 ranges = <0x0 0xf801c000 0x800>; 673 #address-cells = <1>; 674 #size-cells = <1>; 675 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 676 status = "disabled"; 677 678 uart0: serial@200 { 679 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 680 reg = <0x200 0x200>; 681 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 682 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 683 clock-names = "usart"; 684 dmas = <&dma0 685 (AT91_XDMAC_DT_MEM_IF(0) | 686 AT91_XDMAC_DT_PER_IF(1) | 687 AT91_XDMAC_DT_PERID(0))>, 688 <&dma0 689 (AT91_XDMAC_DT_MEM_IF(0) | 690 AT91_XDMAC_DT_PER_IF(1) | 691 AT91_XDMAC_DT_PERID(1))>; 692 dma-names = "tx", "rx"; 693 atmel,use-dma-rx; 694 atmel,use-dma-tx; 695 atmel,fifo-size = <16>; 696 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 697 status = "disabled"; 698 }; 699 700 spi0: spi@400 { 701 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 702 reg = <0x400 0x200>; 703 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 704 #address-cells = <1>; 705 #size-cells = <0>; 706 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 707 clock-names = "spi_clk"; 708 dmas = <&dma0 709 (AT91_XDMAC_DT_MEM_IF(0) | 710 AT91_XDMAC_DT_PER_IF(1) | 711 AT91_XDMAC_DT_PERID(0))>, 712 <&dma0 713 (AT91_XDMAC_DT_MEM_IF(0) | 714 AT91_XDMAC_DT_PER_IF(1) | 715 AT91_XDMAC_DT_PERID(1))>; 716 dma-names = "tx", "rx"; 717 atmel,fifo-size = <16>; 718 status = "disabled"; 719 }; 720 721 i2c0: i2c@600 { 722 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 723 reg = <0x600 0x200>; 724 interrupts = <5 IRQ_TYPE_LEVEL_HIGH 7>; 725 #address-cells = <1>; 726 #size-cells = <0>; 727 clocks = <&pmc PMC_TYPE_PERIPHERAL 5>; 728 dmas = <&dma0 729 (AT91_XDMAC_DT_MEM_IF(0) | 730 AT91_XDMAC_DT_PER_IF(1) | 731 AT91_XDMAC_DT_PERID(0))>, 732 <&dma0 733 (AT91_XDMAC_DT_MEM_IF(0) | 734 AT91_XDMAC_DT_PER_IF(1) | 735 AT91_XDMAC_DT_PERID(1))>; 736 dma-names = "tx", "rx"; 737 atmel,fifo-size = <16>; 738 status = "disabled"; 739 }; 740 }; 741 742 flx1: flexcom@f8020000 { 743 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 744 reg = <0xf8020000 0x200>; 745 ranges = <0x0 0xf8020000 0x800>; 746 #address-cells = <1>; 747 #size-cells = <1>; 748 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 749 status = "disabled"; 750 751 uart1: serial@200 { 752 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 753 reg = <0x200 0x200>; 754 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 755 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 756 clock-names = "usart"; 757 dmas = <&dma0 758 (AT91_XDMAC_DT_MEM_IF(0) | 759 AT91_XDMAC_DT_PER_IF(1) | 760 AT91_XDMAC_DT_PERID(2))>, 761 <&dma0 762 (AT91_XDMAC_DT_MEM_IF(0) | 763 AT91_XDMAC_DT_PER_IF(1) | 764 AT91_XDMAC_DT_PERID(3))>; 765 dma-names = "tx", "rx"; 766 atmel,use-dma-rx; 767 atmel,use-dma-tx; 768 atmel,fifo-size = <16>; 769 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 770 status = "disabled"; 771 }; 772 773 spi1: spi@400 { 774 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 775 reg = <0x400 0x200>; 776 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 777 #address-cells = <1>; 778 #size-cells = <0>; 779 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 780 clock-names = "spi_clk"; 781 dmas = <&dma0 782 (AT91_XDMAC_DT_MEM_IF(0) | 783 AT91_XDMAC_DT_PER_IF(1) | 784 AT91_XDMAC_DT_PERID(2))>, 785 <&dma0 786 (AT91_XDMAC_DT_MEM_IF(0) | 787 AT91_XDMAC_DT_PER_IF(1) | 788 AT91_XDMAC_DT_PERID(3))>; 789 dma-names = "tx", "rx"; 790 atmel,fifo-size = <16>; 791 status = "disabled"; 792 }; 793 794 i2c1: i2c@600 { 795 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 796 reg = <0x600 0x200>; 797 interrupts = <6 IRQ_TYPE_LEVEL_HIGH 7>; 798 #address-cells = <1>; 799 #size-cells = <0>; 800 clocks = <&pmc PMC_TYPE_PERIPHERAL 6>; 801 dmas = <&dma0 802 (AT91_XDMAC_DT_MEM_IF(0) | 803 AT91_XDMAC_DT_PER_IF(1) | 804 AT91_XDMAC_DT_PERID(2))>, 805 <&dma0 806 (AT91_XDMAC_DT_MEM_IF(0) | 807 AT91_XDMAC_DT_PER_IF(1) | 808 AT91_XDMAC_DT_PERID(3))>; 809 dma-names = "tx", "rx"; 810 atmel,fifo-size = <16>; 811 status = "disabled"; 812 }; 813 }; 814 815 flx2: flexcom@f8024000 { 816 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 817 reg = <0xf8024000 0x200>; 818 ranges = <0x0 0xf8024000 0x800>; 819 #address-cells = <1>; 820 #size-cells = <1>; 821 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 822 status = "disabled"; 823 824 uart2: serial@200 { 825 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 826 reg = <0x200 0x200>; 827 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 828 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 829 clock-names = "usart"; 830 dmas = <&dma0 831 (AT91_XDMAC_DT_MEM_IF(0) | 832 AT91_XDMAC_DT_PER_IF(1) | 833 AT91_XDMAC_DT_PERID(4))>, 834 <&dma0 835 (AT91_XDMAC_DT_MEM_IF(0) | 836 AT91_XDMAC_DT_PER_IF(1) | 837 AT91_XDMAC_DT_PERID(5))>; 838 dma-names = "tx", "rx"; 839 atmel,use-dma-rx; 840 atmel,use-dma-tx; 841 atmel,fifo-size = <16>; 842 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 843 status = "disabled"; 844 }; 845 846 spi2: spi@400 { 847 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 848 reg = <0x400 0x200>; 849 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 850 #address-cells = <1>; 851 #size-cells = <0>; 852 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 853 clock-names = "spi_clk"; 854 dmas = <&dma0 855 (AT91_XDMAC_DT_MEM_IF(0) | 856 AT91_XDMAC_DT_PER_IF(1) | 857 AT91_XDMAC_DT_PERID(4))>, 858 <&dma0 859 (AT91_XDMAC_DT_MEM_IF(0) | 860 AT91_XDMAC_DT_PER_IF(1) | 861 AT91_XDMAC_DT_PERID(5))>; 862 dma-names = "tx", "rx"; 863 atmel,fifo-size = <16>; 864 status = "disabled"; 865 }; 866 867 i2c2: i2c@600 { 868 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 869 reg = <0x600 0x200>; 870 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 7>; 871 #address-cells = <1>; 872 #size-cells = <0>; 873 clocks = <&pmc PMC_TYPE_PERIPHERAL 7>; 874 dmas = <&dma0 875 (AT91_XDMAC_DT_MEM_IF(0) | 876 AT91_XDMAC_DT_PER_IF(1) | 877 AT91_XDMAC_DT_PERID(4))>, 878 <&dma0 879 (AT91_XDMAC_DT_MEM_IF(0) | 880 AT91_XDMAC_DT_PER_IF(1) | 881 AT91_XDMAC_DT_PERID(5))>; 882 dma-names = "tx", "rx"; 883 atmel,fifo-size = <16>; 884 status = "disabled"; 885 }; 886 }; 887 888 flx3: flexcom@f8028000 { 889 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 890 reg = <0xf8028000 0x200>; 891 ranges = <0x0 0xf8028000 0x800>; 892 #address-cells = <1>; 893 #size-cells = <1>; 894 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 895 status = "disabled"; 896 897 uart3: serial@200 { 898 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 899 reg = <0x200 0x200>; 900 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 901 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 902 clock-names = "usart"; 903 dmas = <&dma0 904 (AT91_XDMAC_DT_MEM_IF(0) | 905 AT91_XDMAC_DT_PER_IF(1) | 906 AT91_XDMAC_DT_PERID(6))>, 907 <&dma0 908 (AT91_XDMAC_DT_MEM_IF(0) | 909 AT91_XDMAC_DT_PER_IF(1) | 910 AT91_XDMAC_DT_PERID(7))>; 911 dma-names = "tx", "rx"; 912 atmel,use-dma-rx; 913 atmel,use-dma-tx; 914 atmel,fifo-size = <16>; 915 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 916 status = "disabled"; 917 }; 918 919 spi3: spi@400 { 920 compatible = "microchip,sam9x7-spi", "atmel,at91rm9200-spi"; 921 reg = <0x400 0x200>; 922 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 923 #address-cells = <1>; 924 #size-cells = <0>; 925 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 926 clock-names = "spi_clk"; 927 dmas = <&dma0 928 (AT91_XDMAC_DT_MEM_IF(0) | 929 AT91_XDMAC_DT_PER_IF(1) | 930 AT91_XDMAC_DT_PERID(6))>, 931 <&dma0 932 (AT91_XDMAC_DT_MEM_IF(0) | 933 AT91_XDMAC_DT_PER_IF(1) | 934 AT91_XDMAC_DT_PERID(7))>; 935 dma-names = "tx", "rx"; 936 atmel,fifo-size = <16>; 937 status = "disabled"; 938 }; 939 940 i2c3: i2c@600 { 941 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 942 reg = <0x600 0x200>; 943 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 7>; 944 #address-cells = <1>; 945 #size-cells = <0>; 946 clocks = <&pmc PMC_TYPE_PERIPHERAL 8>; 947 dmas = <&dma0 948 (AT91_XDMAC_DT_MEM_IF(0) | 949 AT91_XDMAC_DT_PER_IF(1) | 950 AT91_XDMAC_DT_PERID(6))>, 951 <&dma0 952 (AT91_XDMAC_DT_MEM_IF(0) | 953 AT91_XDMAC_DT_PER_IF(1) | 954 AT91_XDMAC_DT_PERID(7))>; 955 dma-names = "tx", "rx"; 956 atmel,fifo-size = <16>; 957 status = "disabled"; 958 }; 959 }; 960 961 gmac: ethernet@f802c000 { 962 compatible = "microchip,sam9x7-gem", "microchip,sama7g5-gem"; 963 reg = <0xf802c000 0x1000>; 964 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 0 */ 965 <60 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 1 */ 966 <61 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 2 */ 967 <62 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 3 */ 968 <63 IRQ_TYPE_LEVEL_HIGH 3>, /* Queue 4 */ 969 <64 IRQ_TYPE_LEVEL_HIGH 3>; /* Queue 5 */ 970 clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_GCK 24>, <&pmc PMC_TYPE_GCK 67>; 971 clock-names = "hclk", "pclk", "tx_clk", "tsu_clk"; 972 assigned-clocks = <&pmc PMC_TYPE_GCK 67>; 973 assigned-clock-rates = <266666666>; 974 status = "disabled"; 975 }; 976 977 pwm0: pwm@f8034000 { 978 compatible = "microchip,sam9x7-pwm", "microchip,sam9x60-pwm"; 979 reg = <0xf8034000 0x300>; 980 interrupts = <18 IRQ_TYPE_LEVEL_HIGH 4>; 981 clocks = <&pmc PMC_TYPE_PERIPHERAL 18>; 982 #pwm-cells = <3>; 983 status = "disabled"; 984 }; 985 986 flx9: flexcom@f8040000 { 987 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 988 reg = <0xf8040000 0x200>; 989 ranges = <0x0 0xf8040000 0x800>; 990 #address-cells = <1>; 991 #size-cells = <1>; 992 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 993 status = "disabled"; 994 995 uart9: serial@200 { 996 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 997 reg = <0x200 0x200>; 998 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 999 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1000 clock-names = "usart"; 1001 dmas = <&dma0 1002 (AT91_XDMAC_DT_MEM_IF(0) | 1003 AT91_XDMAC_DT_PER_IF(1) | 1004 AT91_XDMAC_DT_PERID(18))>, 1005 <&dma0 1006 (AT91_XDMAC_DT_MEM_IF(0) | 1007 AT91_XDMAC_DT_PER_IF(1) | 1008 AT91_XDMAC_DT_PERID(19))>; 1009 dma-names = "tx", "rx"; 1010 atmel,use-dma-rx; 1011 atmel,use-dma-tx; 1012 atmel,fifo-size = <16>; 1013 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1014 status = "disabled"; 1015 }; 1016 1017 i2c9: i2c@600 { 1018 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 1019 reg = <0x600 0x200>; 1020 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 7>; 1021 #address-cells = <1>; 1022 #size-cells = <0>; 1023 clocks = <&pmc PMC_TYPE_PERIPHERAL 15>; 1024 dmas = <&dma0 1025 (AT91_XDMAC_DT_MEM_IF(0) | 1026 AT91_XDMAC_DT_PER_IF(1) | 1027 AT91_XDMAC_DT_PERID(18))>, 1028 <&dma0 1029 (AT91_XDMAC_DT_MEM_IF(0) | 1030 AT91_XDMAC_DT_PER_IF(1) | 1031 AT91_XDMAC_DT_PERID(19))>; 1032 dma-names = "tx", "rx"; 1033 atmel,fifo-size = <16>; 1034 status = "disabled"; 1035 }; 1036 }; 1037 1038 flx10: flexcom@f8044000 { 1039 compatible = "microchip,sam9x7-flexcom", "atmel,sama5d2-flexcom"; 1040 reg = <0xf8044000 0x200>; 1041 ranges = <0x0 0xf8044000 0x800>; 1042 #address-cells = <1>; 1043 #size-cells = <1>; 1044 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1045 status = "disabled"; 1046 1047 uart10: serial@200 { 1048 compatible = "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 1049 reg = <0x200 0x200>; 1050 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1051 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1052 clock-names = "usart"; 1053 dmas = <&dma0 1054 (AT91_XDMAC_DT_MEM_IF(0) | 1055 AT91_XDMAC_DT_PER_IF(1) | 1056 AT91_XDMAC_DT_PERID(20))>, 1057 <&dma0 1058 (AT91_XDMAC_DT_MEM_IF(0) | 1059 AT91_XDMAC_DT_PER_IF(1) | 1060 AT91_XDMAC_DT_PERID(21))>; 1061 dma-names = "tx", "rx"; 1062 atmel,use-dma-rx; 1063 atmel,use-dma-tx; 1064 atmel,fifo-size = <16>; 1065 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1066 status = "disabled"; 1067 }; 1068 1069 i2c10: i2c@600 { 1070 compatible = "microchip,sam9x7-i2c", "microchip,sam9x60-i2c"; 1071 reg = <0x600 0x200>; 1072 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 7>; 1073 #address-cells = <1>; 1074 #size-cells = <0>; 1075 clocks = <&pmc PMC_TYPE_PERIPHERAL 16>; 1076 dmas = <&dma0 1077 (AT91_XDMAC_DT_MEM_IF(0) | 1078 AT91_XDMAC_DT_PER_IF(1) | 1079 AT91_XDMAC_DT_PERID(20))>, 1080 <&dma0 1081 (AT91_XDMAC_DT_MEM_IF(0) | 1082 AT91_XDMAC_DT_PER_IF(1) | 1083 AT91_XDMAC_DT_PERID(21))>; 1084 dma-names = "tx", "rx"; 1085 atmel,fifo-size = <16>; 1086 status = "disabled"; 1087 }; 1088 }; 1089 1090 matrix: matrix@ffffde00 { 1091 compatible = "microchip,sam9x7-matrix", "atmel,at91sam9x5-matrix", "syscon"; 1092 reg = <0xffffde00 0x200>; 1093 }; 1094 1095 pmecc: ecc-engine@ffffe000 { 1096 compatible = "microchip,sam9x7-pmecc", "atmel,at91sam9g45-pmecc"; 1097 reg = <0xffffe000 0x300>, <0xffffe600 0x100>; 1098 }; 1099 1100 mpddrc: mpddrc@ffffe800 { 1101 compatible = "microchip,sam9x7-ddramc", "atmel,sama5d3-ddramc"; 1102 reg = <0xffffe800 0x200>; 1103 clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>; 1104 clock-names = "ddrck", "mpddr"; 1105 }; 1106 1107 smc: smc@ffffea00 { 1108 compatible = "microchip,sam9x7-smc", "atmel,at91sam9260-smc", "syscon"; 1109 reg = <0xffffea00 0x100>; 1110 }; 1111 1112 aic: interrupt-controller@fffff100 { 1113 compatible = "microchip,sam9x7-aic"; 1114 reg = <0xfffff100 0x100>; 1115 #interrupt-cells = <3>; 1116 interrupt-controller; 1117 atmel,external-irqs = <31>; 1118 }; 1119 1120 dbgu: serial@fffff200 { 1121 compatible = "microchip,sam9x7-dbgu", "atmel,at91sam9260-dbgu", "microchip,sam9x7-usart", "atmel,at91sam9260-usart"; 1122 reg = <0xfffff200 0x200>; 1123 interrupts = <47 IRQ_TYPE_LEVEL_HIGH 7>; 1124 clocks = <&pmc PMC_TYPE_PERIPHERAL 47>; 1125 clock-names = "usart"; 1126 dmas = <&dma0 1127 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1128 AT91_XDMAC_DT_PERID(28))>, 1129 <&dma0 1130 (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) | 1131 AT91_XDMAC_DT_PERID(29))>; 1132 dma-names = "tx", "rx"; 1133 atmel,usart-mode = <AT91_USART_MODE_SERIAL>; 1134 status = "disabled"; 1135 }; 1136 1137 pinctrl: pinctrl@fffff400 { 1138 compatible = "microchip,sam9x7-pinctrl", "microchip,sam9x60-pinctrl", "simple-mfd"; 1139 ranges = <0xfffff400 0xfffff400 0x800>; 1140 #address-cells = <1>; 1141 #size-cells = <1>; 1142 1143 /* mux-mask corresponding to sam9x7 SoC in TFBGA228L package */ 1144 atmel,mux-mask = < 1145 /* A B C D */ 1146 0xffffffff 0xffffefc0 0xc0ffd000 0x00000000 /* pioA */ 1147 0x07ffffff 0x0805fe7f 0x01ff9f81 0x06078000 /* pioB */ 1148 0xffffffff 0x07dfffff 0xfa3fffff 0x00000000 /* pioC */ 1149 0x00003fff 0x00003fe0 0x0000003f 0x00000000 /* pioD */ 1150 >; 1151 1152 pioA: gpio@fffff400 { 1153 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1154 reg = <0xfffff400 0x200>; 1155 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>; 1156 #interrupt-cells = <2>; 1157 interrupt-controller; 1158 #gpio-cells = <2>; 1159 gpio-controller; 1160 clocks = <&pmc PMC_TYPE_PERIPHERAL 2>; 1161 }; 1162 1163 pioB: gpio@fffff600 { 1164 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1165 reg = <0xfffff600 0x200>; 1166 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>; 1167 #interrupt-cells = <2>; 1168 interrupt-controller; 1169 #gpio-cells = <2>; 1170 gpio-controller; 1171 #gpio-lines = <26>; 1172 clocks = <&pmc PMC_TYPE_PERIPHERAL 3>; 1173 }; 1174 1175 pioC: gpio@fffff800 { 1176 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1177 reg = <0xfffff800 0x200>; 1178 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>; 1179 #interrupt-cells = <2>; 1180 interrupt-controller; 1181 #gpio-cells = <2>; 1182 gpio-controller; 1183 clocks = <&pmc PMC_TYPE_PERIPHERAL 4>; 1184 }; 1185 1186 pioD: gpio@fffffa00 { 1187 compatible = "microchip,sam9x7-gpio", "microchip,sam9x60-gpio", "atmel,at91rm9200-gpio"; 1188 reg = <0xfffffa00 0x200>; 1189 interrupts = <44 IRQ_TYPE_LEVEL_HIGH 1>; 1190 #interrupt-cells = <2>; 1191 interrupt-controller; 1192 #gpio-cells = <2>; 1193 gpio-controller; 1194 #gpio-lines = <22>; 1195 clocks = <&pmc PMC_TYPE_PERIPHERAL 44>; 1196 }; 1197 }; 1198 1199 pmc: clock-controller@fffffc00 { 1200 compatible = "microchip,sam9x7-pmc", "syscon"; 1201 reg = <0xfffffc00 0x200>; 1202 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1203 #clock-cells = <2>; 1204 clocks = <&clk32k 1>, <&clk32k 0>, <&main_xtal>; 1205 clock-names = "td_slck", "md_slck", "main_xtal"; 1206 }; 1207 1208 reset_controller: reset-controller@fffffe00 { 1209 compatible = "microchip,sam9x7-rstc", "microchip,sam9x60-rstc"; 1210 reg = <0xfffffe00 0x10>; 1211 clocks = <&clk32k 0>; 1212 }; 1213 1214 poweroff: poweroff@fffffe10 { 1215 compatible = "microchip,sam9x7-shdwc", "microchip,sam9x60-shdwc"; 1216 reg = <0xfffffe10 0x10>; 1217 #address-cells = <1>; 1218 #size-cells = <0>; 1219 clocks = <&clk32k 0>; 1220 atmel,wakeup-rtc-timer; 1221 atmel,wakeup-rtt-timer; 1222 status = "disabled"; 1223 }; 1224 1225 rtt: rtc@fffffe20 { 1226 compatible = "microchip,sam9x7-rtt", "atmel,at91sam9260-rtt"; 1227 reg = <0xfffffe20 0x20>; 1228 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1229 clocks = <&clk32k 0>; 1230 }; 1231 1232 clk32k: clock-controller@fffffe50 { 1233 compatible = "microchip,sam9x7-sckc", "microchip,sam9x60-sckc"; 1234 reg = <0xfffffe50 0x4>; 1235 clocks = <&slow_xtal>; 1236 #clock-cells = <1>; 1237 }; 1238 1239 gpbr: syscon@fffffe60 { 1240 compatible = "microchip,sam9x7-gpbr", "atmel,at91sam9260-gpbr", "syscon"; 1241 reg = <0xfffffe60 0x10>; 1242 }; 1243 1244 rtc: rtc@fffffea8 { 1245 compatible = "microchip,sam9x7-rtc", "microchip,sam9x60-rtc"; 1246 reg = <0xfffffea8 0x100>; 1247 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1248 clocks = <&clk32k 0>; 1249 }; 1250 1251 watchdog: watchdog@ffffff80 { 1252 compatible = "microchip,sam9x7-wdt", "microchip,sam9x60-wdt"; 1253 reg = <0xffffff80 0x24>; 1254 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>; 1255 status = "disabled"; 1256 }; 1257 }; 1258}; 1259