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/linux-6.14.4/drivers/clk/hisilicon/
Dclk-hi3519.c35 { HI3519_FIXED_24M, "24m", NULL, 0, 24000000, },
36 { HI3519_FIXED_50M, "50m", NULL, 0, 50000000, },
37 { HI3519_FIXED_75M, "75m", NULL, 0, 75000000, },
38 { HI3519_FIXED_125M, "125m", NULL, 0, 125000000, },
39 { HI3519_FIXED_150M, "150m", NULL, 0, 150000000, },
40 { HI3519_FIXED_200M, "200m", NULL, 0, 200000000, },
41 { HI3519_FIXED_250M, "250m", NULL, 0, 250000000, },
42 { HI3519_FIXED_300M, "300m", NULL, 0, 300000000, },
43 { HI3519_FIXED_400M, "400m", NULL, 0, 400000000, },
47 "24m", "75m", "125m", "150m", "200m", "250m", "300m", "400m", };
[all …]
Dclk-hi3559a.c23 #define PLL_MASK_WIDTH 24
62 { HI3559AV100_FIXED_1188M, "1188m", NULL, 0, 1188000000, },
63 { HI3559AV100_FIXED_1000M, "1000m", NULL, 0, 1000000000, },
64 { HI3559AV100_FIXED_842M, "842m", NULL, 0, 842000000, },
65 { HI3559AV100_FIXED_792M, "792m", NULL, 0, 792000000, },
66 { HI3559AV100_FIXED_750M, "750m", NULL, 0, 750000000, },
67 { HI3559AV100_FIXED_710M, "710m", NULL, 0, 710000000, },
68 { HI3559AV100_FIXED_680M, "680m", NULL, 0, 680000000, },
69 { HI3559AV100_FIXED_667M, "667m", NULL, 0, 667000000, },
70 { HI3559AV100_FIXED_631M, "631m", NULL, 0, 631000000, },
[all …]
Dcrg-hi3798cv200.c48 { HI3798CV200_FIXED_12M, "12m", NULL, 0, 12000000, },
49 { HI3798CV200_FIXED_24M, "24m", NULL, 0, 24000000, },
50 { HI3798CV200_FIXED_25M, "25m", NULL, 0, 25000000, },
51 { HI3798CV200_FIXED_48M, "48m", NULL, 0, 48000000, },
52 { HI3798CV200_FIXED_50M, "50m", NULL, 0, 50000000, },
53 { HI3798CV200_FIXED_60M, "60m", NULL, 0, 60000000, },
54 { HI3798CV200_FIXED_75M, "75m", NULL, 0, 75000000, },
55 { HI3798CV200_FIXED_100M, "100m", NULL, 0, 100000000, },
56 { HI3798CV200_FIXED_150M, "150m", NULL, 0, 150000000, },
58 { HI3798CV200_FIXED_200M, "200m", NULL, 0, 200000000, },
[all …]
Dcrg-hi3516cv300.c40 { HI3516CV300_FIXED_3M, "3m", NULL, 0, 3000000, },
41 { HI3516CV300_FIXED_6M, "6m", NULL, 0, 6000000, },
42 { HI3516CV300_FIXED_24M, "24m", NULL, 0, 24000000, },
43 { HI3516CV300_FIXED_49P5, "49.5m", NULL, 0, 49500000, },
44 { HI3516CV300_FIXED_50M, "50m", NULL, 0, 50000000, },
45 { HI3516CV300_FIXED_83P3M, "83.3m", NULL, 0, 83300000, },
46 { HI3516CV300_FIXED_99M, "99m", NULL, 0, 99000000, },
47 { HI3516CV300_FIXED_100M, "100m", NULL, 0, 100000000, },
48 { HI3516CV300_FIXED_148P5M, "148.5m", NULL, 0, 148500000, },
49 { HI3516CV300_FIXED_198M, "198m", NULL, 0, 198000000, },
[all …]
/linux-6.14.4/drivers/clk/sunxi-ng/
Dccu-sun50i-a100.c25 #define SUN50I_A100_PLL_SDM_ENABLE BIT(24)
39 * The M factor is present in the register's description, but not in the
40 * frequency formula, and it's documented as "M is only used for backdoor
62 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
78 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
95 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
113 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
132 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
148 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
164 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
[all …]
Dccu-sun50i-h6.c31 * The M factor is present in the register's description, but not in the
32 * frequency formula, and it's documented as "M is only used for backdoor
54 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
69 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
86 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
104 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
122 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
140 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
158 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
173 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
[all …]
Dccu-sun20i-d1.c55 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
70 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
84 static SUNXI_CCU_M_HWS(pll_periph0_800M_clk, "pll-periph0-800M",
106 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
130 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
154 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
165 * PLL_AUDIO0 has m0, m1 dividers in addition to the usual N, M factors.
168 * The M factor must be an even number to produce a 50% duty cycle output.
172 { .rate = 90316800, .pattern = 0xc001288d, .m = 6, .n = 22 },
179 .m = _SUNXI_CCU_DIV(16, 6),
[all …]
Dccu-sun50i-h616.c33 * The M factor is present in the register's description, but not in the
34 * frequency formula, and it's documented as "M is only used for backdoor
56 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
71 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
86 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
103 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
120 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
139 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
157 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
175 .m = _SUNXI_CCU_DIV(1, 1), /* input divider */
[all …]
Dccu-sun9i-a80.c64 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
74 .m = _SUNXI_CCU_DIV_OFFSET(0, 6, 0),
89 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
105 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
121 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
137 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
152 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
168 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
184 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
200 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
[all …]
Dccu-sun8i-r40.c33 .m = _SUNXI_CCU_DIV(0, 2),
59 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
60 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
66 0, 5, /* M */
67 pll_audio_sdm_table, BIT(24),
78 0, 4, /* M */
79 BIT(24), /* frac enable */
87 /* TODO: The result of N/M is required to be in [8, 25] range. */
91 0, 4, /* M */
92 BIT(24), /* frac enable */
[all …]
Dccu-sun6i-a31.c36 0, 2, /* M */
56 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
57 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
63 0, 5, /* M */
64 pll_audio_sdm_table, BIT(24),
73 0, 4, /* M */
74 BIT(24), /* frac enable */
85 0, 4, /* M */
86 BIT(24), /* frac enable */
98 0, 2, /* M */
[all …]
Dccu-sun8i-a33.c32 .m = _SUNXI_CCU_DIV(0, 2),
58 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
59 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
65 0, 5, /* M */
66 pll_audio_sdm_table, BIT(24),
75 0, 4, /* M */
76 BIT(24), /* frac enable */
87 0, 4, /* M */
88 BIT(24), /* frac enable */
100 0, 2, /* M */
[all …]
Dccu-sun8i-a23.c34 .m = _SUNXI_CCU_DIV(0, 2),
60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
67 0, 5, /* M */
68 pll_audio_sdm_table, BIT(24),
77 0, 4, /* M */
78 BIT(24), /* frac enable */
89 0, 4, /* M */
90 BIT(24), /* frac enable */
102 0, 2, /* M */
[all …]
Dccu-sun50i-a64.c31 .m = _SUNXI_CCU_DIV(0, 2),
57 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
58 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
64 0, 5, /* M */
65 pll_audio_sdm_table, BIT(24),
76 0, 4, /* M */
77 BIT(24), /* frac enable */
88 0, 4, /* M */
89 BIT(24), /* frac enable */
101 0, 2, /* M */
[all …]
Dccu-sun8i-a83t.c65 * The Audio PLL has d1, d2 dividers in addition to the usual N, M
74 { .rate = 45158400, .pattern = 0xc00121ff, .m = 29, .n = 54 },
75 { .rate = 49152000, .pattern = 0xc000e147, .m = 30, .n = 61 },
82 .m = _SUNXI_CCU_DIV(0, 6),
84 .sdm = _SUNXI_CCU_SDM(pll_audio_sdm_table, BIT(24),
102 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
119 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
135 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
151 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
167 .m = _SUNXI_CCU_DIV(16, 1), /* input divider */
[all …]
Dccu-sun4i-a10.c34 .m = _SUNXI_CCU_DIV(0, 2),
60 { .rate = 22579200, .pattern = 0xc0010d84, .m = 8, .n = 7 },
61 { .rate = 24576000, .pattern = 0xc000ac02, .m = 14, .n = 14 },
67 .m = _SUNXI_CCU_DIV_OFFSET(0, 5, 0),
102 .m = _SUNXI_CCU_DIV(0, 2),
286 0, 5, /* M */
288 24, 2, /* mux */
341 0x060, BIT(24), 0);
452 0, 4, /* M */
454 24, 2, /* mux */
[all …]
/linux-6.14.4/include/linux/isdn/
Dcapiutil.h1 /* $Id: capiutil.h,v 1.5.6.2 2001/09/23 22:24:33 kai Exp $
19 #define CAPIMSG_U8(m, off) (m[off]) argument
20 #define CAPIMSG_U16(m, off) (m[off]|(m[(off)+1]<<8)) argument
21 #define CAPIMSG_U32(m, off) (m[off]|(m[(off)+1]<<8)|(m[(off)+2]<<16)|(m[(off)+3]<<24)) argument
22 #define CAPIMSG_LEN(m) CAPIMSG_U16(m,0) argument
23 #define CAPIMSG_APPID(m) CAPIMSG_U16(m,2) argument
24 #define CAPIMSG_COMMAND(m) CAPIMSG_U8(m,4) argument
25 #define CAPIMSG_SUBCOMMAND(m) CAPIMSG_U8(m,5) argument
26 #define CAPIMSG_CMD(m) (((m[4])<<8)|(m[5])) argument
27 #define CAPIMSG_MSGID(m) CAPIMSG_U16(m,6) argument
[all …]
/linux-6.14.4/drivers/media/platform/ti/cal/
Dcal_regs.h43 #define CAL_HL_IRQSTATUS_RAW(m) (0x20U + (m) * 0x10U) argument
44 #define CAL_HL_IRQSTATUS(m) (0x24U + (m) * 0x10U) argument
45 #define CAL_HL_IRQENABLE_SET(m) (0x28U + (m) * 0x10U) argument
46 #define CAL_HL_IRQENABLE_CLR(m) (0x2cU + (m) * 0x10U) argument
47 #define CAL_PIX_PROC(m) (0xc0U + (m) * 0x4U) argument
63 #define CAL_WR_DMA_CTRL(m) (0x200U + (m) * 0x10U) argument
64 #define CAL_WR_DMA_ADDR(m) (0x204U + (m) * 0x10U) argument
65 #define CAL_WR_DMA_OFST(m) (0x208U + (m) * 0x10U) argument
66 #define CAL_WR_DMA_XSIZE(m) (0x20cU + (m) * 0x10U) argument
67 #define CAL_CSI2_PPI_CTRL(m) (0x300U + (m) * 0x80U) argument
[all …]
/linux-6.14.4/drivers/clk/sunxi/
Dclk-sun9i-core.c18 * sun9i_a80_get_pll4_factors() - calculates n, p, m factors for PLL4
20 * rate = (parent_rate * n >> p) / (m + 1);
21 * parent_rate is always 24MHz
23 * p and m are named div1 and div2 in Allwinner's SDK
29 int m = 1; in sun9i_a80_get_pll4_factors() local
32 /* Normalize value to a 6 MHz multiple (24 MHz / 4) */ in sun9i_a80_get_pll4_factors()
37 m = 0; in sun9i_a80_get_pll4_factors()
41 /* If n is still too large switch to steps of 24 MHz */ in sun9i_a80_get_pll4_factors()
53 req->rate = ((24000000 * n) >> p) / (m + 1); in sun9i_a80_get_pll4_factors()
55 req->m = m; in sun9i_a80_get_pll4_factors()
[all …]
Dclk-sunxi.c27 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
29 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
30 * parent_rate is always 24Mhz
37 /* Normalize value to a 6M multiple */ in sun4i_get_pll1_factors()
41 /* m is always zero for pll1 */ in sun4i_get_pll1_factors()
42 req->m = 0; in sun4i_get_pll1_factors()
75 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
77 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
78 * parent_rate should always be 24MHz
118 * 3, m is 3. This is the first time we use 6 here, yet we in sun6i_a31_get_pll1_factors()
[all …]
/linux-6.14.4/Documentation/mm/damon/
Dmonitoring_intervals_tuning_example.rst102 0 addr 10.180 GiB size 6.117 GiB access 0 % age 7 m 8 s # coldest
103 1 addr 49.275 GiB size 6.195 GiB access 0 % age 6 m 14 s
104 2 addr 62.421 GiB size 3.579 GiB access 0 % age 6 m 4 s
105 3 addr 40.154 GiB size 6.127 GiB access 0 % age 5 m 40 s
106 4 addr 16.296 GiB size 6.182 GiB access 0 % age 5 m 32 s
107 5 addr 34.254 GiB size 5.899 GiB access 0 % age 5 m 24 s
108 6 addr 46.281 GiB size 2.995 GiB access 0 % age 5 m 20 s
109 7 addr 28.420 GiB size 5.835 GiB access 0 % age 5 m 6 s
110 8 addr 4.000 GiB size 6.180 GiB access 0 % age 4 m 16 s
111 9 addr 22.478 GiB size 5.942 GiB access 0 % age 3 m 58 s
[all …]
/linux-6.14.4/sound/firewire/
DKconfig28 * Focusrite Saffire Pro 14, Pro 24, Pro 24 DSP, Pro 26, Pro 40(TCD2220)
31 * M-Audio ProFire 610/2626
37 * TC Electronic Studio Konnekt 48, Konnekt 24D, Konnekt Live, Impact Twin
41 To compile this driver as a module, choose M here: the module
64 To compile this driver as a module, choose M here: the module
74 To compile this driver as a module, choose M here: the module
90 To compile this driver as a module, choose M here: the module
116 * Phonic Helix Board 12 MkII/18 MkII/24 MkII
117 * Phonic Helix Board 12 Universal/18 Universal/24 Universal
121 * TerraTec PHASE 24 FW/PHASE X24 FW/PHASE 88 Rack FW
[all …]
/linux-6.14.4/fs/bcachefs/
Dtime_stats.c18 { "m", (u64) NSEC_PER_SEC * 60},
20 { "d", (u64) NSEC_PER_SEC * 3600 * 24},
21 { "w", (u64) NSEC_PER_SEC * 3600 * 24 * 7},
22 …{ "y", (u64) NSEC_PER_SEC * ((3600 * 24 * 7 * 365) + (3600 * (24 / 4) * 7))}, /* 365.25d …
47 e->m = v; in quantiles_update()
49 } else if (e->m > v) { in quantiles_update()
50 e->m = e->m >= e->step in quantiles_update()
51 ? e->m - e->step in quantiles_update()
53 } else if (e->m < v) { in quantiles_update()
54 e->m = e->m + e->step > e->m in quantiles_update()
[all …]
/linux-6.14.4/drivers/misc/genwqe/
Dcard_utils.c145 char ch = (char)((app_id >> (24 - j*8)) & 0xff); in genwqe_read_app_id()
171 crc = i << 24; in genwqe_init_crc32()
204 i = ((crc >> 24) ^ *buff++) & 0xFF; in genwqe_crc32()
525 * @m: mapping params
545 int genwqe_user_vmap(struct genwqe_dev *cd, struct dma_mapping *m, void *uaddr, in genwqe_user_vmap() argument
553 m->size = 0; /* mark unused and not added */ in genwqe_user_vmap()
556 m->u_vaddr = uaddr; in genwqe_user_vmap()
557 m->size = size; in genwqe_user_vmap()
563 m->size = 0; /* mark unused and not added */ in genwqe_user_vmap()
566 m->nr_pages = DIV_ROUND_UP(offs + size, PAGE_SIZE); in genwqe_user_vmap()
[all …]
/linux-6.14.4/Documentation/userspace-api/media/v4l/
Dmetafmt-generic.rst30 Each cell is one byte. "M" denotes a byte of metadata.
40 - M\ :sub:`00`
41 - M\ :sub:`10`
42 - M\ :sub:`20`
43 - M\ :sub:`30`
45 - M\ :sub:`01`
46 - M\ :sub:`11`
47 - M\ :sub:`21`
48 - M\ :sub:`31`
72 Each cell is one byte. "M" denotes a byte of metadata and "x" a byte of padding.
[all …]

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