| /linux-6.14.4/arch/x86/kvm/ |
| D | lapic.c | 4 * Local APIC virtualization
63 * Enable local APIC timer advancement (tscdeadline mode only) with adaptive
79 static int kvm_lapic_msr_read(struct kvm_lapic *apic, u32 reg, u64 *data);
80 static int kvm_lapic_msr_write(struct kvm_lapic *apic, u32 reg, u64 data);
87 static inline void kvm_lapic_set_reg(struct kvm_lapic *apic, int reg_off, u32 val) in kvm_lapic_set_reg() argument
89 __kvm_lapic_set_reg(apic->regs, reg_off, val); in kvm_lapic_set_reg()
98 static __always_inline u64 kvm_lapic_get_reg64(struct kvm_lapic *apic, int reg) in kvm_lapic_get_reg64() argument
100 return __kvm_lapic_get_reg64(apic->regs, reg); in kvm_lapic_get_reg64()
109 static __always_inline void kvm_lapic_set_reg64(struct kvm_lapic *apic, in kvm_lapic_set_reg64() argument
112 __kvm_lapic_set_reg64(apic->regs, reg, val); in kvm_lapic_set_reg64()
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| D | lapic.h | 73 * APIC register page. The layout matches the register layout seen by
109 int kvm_apic_local_deliver(struct kvm_lapic *apic, int lvt_type);
116 void kvm_apic_send_ipi(struct kvm_lapic *apic, u32 icr_low, u32 icr_high);
134 int kvm_x2apic_icr_write(struct kvm_lapic *apic, u64 data);
144 u64 kvm_lapic_readable_reg_mask(struct kvm_lapic *apic);
159 static inline void kvm_lapic_set_irr(int vec, struct kvm_lapic *apic) in kvm_lapic_set_irr() argument
161 kvm_lapic_set_vector(vec, apic->regs + APIC_IRR); in kvm_lapic_set_irr()
166 apic->irr_pending = true; in kvm_lapic_set_irr()
174 static inline u32 kvm_lapic_get_reg(struct kvm_lapic *apic, int reg_off) in kvm_lapic_get_reg() argument
176 return __kvm_lapic_get_reg(apic->regs, reg_off); in kvm_lapic_get_reg()
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| /linux-6.14.4/arch/x86/kernel/apic/ |
| D | apic.c | 3 * Local APIC handling, local APIC timers
13 * Mikael Pettersson : Power Management for UP-APIC.
53 #include <asm/apic.h>
84 * Hypervisor supports 15 bits of APIC ID in MSI Extended Destination ID
97 /* Local APIC was disabled by the BIOS and enabled by the kernel */
104 * local APIC. Before entering Symmetric I/O Mode, either
110 /* NMI and 8259 INTR go through APIC */ in imcr_pic_to_apic()
122 * Knob to control our willingness to enable the local APIC.
129 * APIC command line parameters
154 /* Disable local APIC timer from the kernel commandline or via dmi quirk */
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| D | init.c | 2 #define pr_fmt(fmt) "APIC: " fmt
4 #include <asm/apic.h>
15 DEFINE_STATIC_CALL_NULL(apic_call_##__cb, *apic->__cb)
41 apic->__cb = __x86_apic_override.__cb
62 static_call_update(apic_call_##__cb, *apic->__cb)
85 /* Ensure that the default APIC has native_eoi populated */ in apic_setup_apic_calls()
86 apic->native_eoi = apic->eoi; in apic_setup_apic_calls()
91 void __init apic_install_driver(struct apic *driver) in apic_install_driver()
93 if (apic == driver) in apic_install_driver()
96 apic = driver; in apic_install_driver()
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| D | io_apic.c | 3 * Intel IO-APIC support for multi-Pentium hosts.
10 * (c) 1999, Multiple IO-APIC support, developed by
25 * - SiS APIC rmw bug:
67 #include <asm/apic.h>
90 int apic, pin; member
112 /* I/O APIC config */
114 /* IO APIC gsi routing info */
193 /* disable IO-APIC */ in parse_noapic()
204 apic_pr_verbose("Int: type %d, pol %d, trig %d, bus %02x, IRQ %02x, APIC ID %x, APIC INT %02x\n", in mp_save_irq()
264 static inline void io_apic_eoi(unsigned int apic, unsigned int vector) in io_apic_eoi() argument
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| D | probe_32.c | 3 * Default generic APIC driver. This handles up to 8 CPUs.
7 * Generic x86 APIC driver probe layer.
16 #include <asm/apic.h>
37 static struct apic apic_default __ro_after_init = {
72 struct apic *apic __ro_after_init = &apic_default;
73 EXPORT_SYMBOL_GPL(apic);
78 struct apic **drv; in parse_apic()
94 early_param("apic", parse_apic);
128 struct apic **drv; in x86_32_probe_apic()
138 panic("Didn't find an APIC driver"); in x86_32_probe_apic()
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| D | apic_noop.c | 3 * NOOP APIC driver.
5 * Does almost nothing and should be substituted by a real apic driver via
8 * Though in case if apic is disabled (for some reason) we try
9 * to not uglify the caller's code and allow to call (some) apic routines
14 * APIC::read/write() have a WARN_ON_ONCE() in them. Sigh...
19 #include <asm/apic.h>
46 struct apic apic_noop __ro_after_init = {
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| D | bigsmp_32.c | 3 * APIC driver for "bigsmp" xAPIC machines with more than 8 virtual CPUs.
5 * Drives the local APIC in "clustered mode".
11 #include <asm/apic.h>
35 printk(KERN_NOTICE "%s detected: force use of apic=bigsmp\n", d->ident); in hp_ht_bigsmp()
62 static struct apic apic_bigsmp __ro_after_init = {
96 return apic == &apic_bigsmp || !cmdline_override; in apic_bigsmp_possible()
101 if (apic != &apic_bigsmp) in apic_bigsmp_force()
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| D | apic_flat_64.c | 5 * Flat APIC subarch code.
13 #include <asm/apic.h>
32 static struct apic apic_physflat __ro_after_init = {
67 struct apic *apic __ro_after_init = &apic_physflat;
68 EXPORT_SYMBOL_GPL(apic);
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| D | vector.c | 3 * Local APIC related interfaces to support IOAPIC, MSI, etc.
6 * Moved from arch/x86/kernel/apic/io_apic.c.
19 #include <asm/apic.h>
136 apicd->hw_irq_cfg.dest_apicid = apic->calc_dest_apicid(cpu); in apic_update_irq_cfg()
665 return fwname && !strncmp(fwname, "IO-APIC-", 8) && in x86_fwspec_is_ioapic()
691 * if IRQ remapping is enabled. APIC IDs above 15 bits are in x86_vector_select()
756 * If the IO/APIC is disabled via config, kernel command line or in lapic_update_legacy_vectors()
786 * in the IO/APIC code. in lapic_assign_system_vectors()
832 /* Online the local APIC infrastructure and initialize the vectors */
926 .name = "APIC",
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| D | probe_64.c | 5 * Generic APIC sub-arch probe layer.
12 #include <asm/apic.h>
16 /* Select the appropriate APIC driver */
19 struct apic **drv; in x86_64_probe_apic()
33 struct apic **drv; in default_acpi_madt_oem_check()
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| D | Makefile | 3 # Makefile for local APIC drivers and for the IO-APIC code
10 obj-$(CONFIG_X86_LOCAL_APIC) += apic.o apic_common.o apic_noop.o ipi.o vector.o init.o
18 # APIC probe will depend on the listing order here
26 # APIC probe will depend on the listing order here
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| D | apic_numachip.c | 6 * Numascale NumaConnect-Specific APIC Code
24 static const struct apic apic_numachip1;
25 static const struct apic apic_numachip2;
76 /* Send via local APIC where non-local part matches */ in numachip_send_IPI_one()
136 return apic == &apic_numachip1; in numachip1_probe()
141 return apic == &apic_numachip2; in numachip2_probe()
205 static const struct apic apic_numachip1 __refconst = {
239 static const struct apic apic_numachip2 __refconst = {
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| /linux-6.14.4/arch/x86/kernel/cpu/ |
| D | topology.c | 3 * CPU/APIC topology
5 * The APIC IDs describe the system topology in multiple domain levels.
7 * APIC ID is associated to the individual levels:
29 #include <asm/apic.h>
38 * Map cpu index to physical APIC ID
88 * Convert the APIC ID to a domain level ID by masking out the low bits
137 * longer supported, the real BSP APIC ID is the first one which is in check_for_real_bsp()
139 * CPU is the real BSP. If it is not, then do not register the APIC in check_for_real_bsp()
143 * The first APIC ID which is enumerated by firmware is detectable in check_for_real_bsp()
144 * because the boot CPU APIC ID is registered before that without in check_for_real_bsp()
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| D | topology_common.c | 7 #include <asm/apic.h>
135 /* Preset Initial APIC ID from CPUID leaf 1 */ in parse_topology()
141 * the APIC is mapped or X2APIC enabled. For establishing the in parse_topology()
142 * topology, that's not required. Use the initial APIC ID. in parse_topology()
210 pr_err(FW_BUG "CPU%4u: APIC ID mismatch. CPUID: 0x%04x APIC: 0x%04x\n", in cpu_parse_topology()
215 pr_err(FW_BUG "CPU%4u: APIC ID mismatch. Firmware: 0x%04x APIC: 0x%04x\n", in cpu_parse_topology()
252 * APIC ID. in cpu_init_topology()
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| /linux-6.14.4/arch/x86/include/asm/ |
| D | apic.h | 35 * up by using apic=verbose for more information and apic=debug for _lots_
36 * of information. apic_verbosity is defined in apic.c
78 * With 82489DX we can't rely on apic feature bit
80 * such an apic chip so we assume that SMP configuration
268 * Generic APIC sub-arch data struct.
274 struct apic { struct
303 /* The limit of the APIC ID space. */
341 * Pointer to the local APIC driver in use on this system (there's
345 extern struct apic *apic;
348 * APIC drivers are probed based on how they are listed in the .apicdrivers
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| /linux-6.14.4/tools/testing/selftests/kvm/x86/ |
| D | apic_bus_clock_test.c | 5 * Verify KVM correctly emulates the APIC bus frequency when the VMM configures
6 * the frequency via KVM_CAP_X86_APIC_BUS_CYCLES_NS. Start the APIC timer by
10 * of the expected value based on the time elapsed, the APIC bus frequency, and
14 #include "apic.h"
18 * Possible TDCR values with matching divide count. Used to modify APIC
146 "Setting of APIC bus frequency after vCPU is created should fail."); in run_apic_bus_clock_test()
158 printf("usage: %s [-h] [-d delay] [-f APIC bus freq]\n", name); in help()
160 printf("-d: Delay (in msec) guest uses to measure APIC bus frequency.\n"); in help()
161 printf("-f: The APIC bus frequency (in MHz) to be configured for the guest.\n"); in help()
168 * Arbitrarilty default to 25MHz for the APIC bus frequency, which is in main()
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| /linux-6.14.4/Documentation/devicetree/bindings/interrupt-controller/ |
| D | intel,ce4100-ioapic.yaml | 7 title: Intel I/O Advanced Programmable Interrupt Controller (IO APIC)
13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
14 family of interrupt controllers. The APIC is a split
16 into the processor itself and an external I/O APIC. Local APIC
18 from internal sources and from an external I/O APIC (ioapic).
26 This schema defines bindings for I/O APIC interrupt controller.
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| D | intel,ce4100-lapic.yaml | 13 Intel's Advanced Programmable Interrupt Controller (APIC) is a
14 family of interrupt controllers. The APIC is a split
16 into the processor itself and an external I/O APIC. Local APIC
18 from internal sources and from an external I/O APIC (ioapic).
26 This schema defines bindings for local APIC interrupt controller.
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| /linux-6.14.4/drivers/iommu/ |
| D | hyperv-iommu.c | 17 #include <asm/apic.h>
30 * According 82093AA IO-APIC spec , IO APIC has a 24-entry Interrupt
31 * Redirection Table. Hyper-V exposes one single IO-APIC and so define
32 * 24 IO APIC remmapping entries.
89 * Hypver-V IO APIC irq affinity should be in the scope of in hyperv_irq_remapping_alloc()
107 /* Claim the only I/O APIC emulated by Hyper-V */ in hyperv_irq_remapping_select()
159 * IO-APIC and so IO-APIC only accepts 8-bit APIC ID. in hyperv_prepare_irq_remapping()
160 * Cpu's APIC ID is read from ACPI MADT table and APIC IDs in hyperv_prepare_irq_remapping()
162 * APIC ID reflects cpu topology. There maybe some APIC ID in hyperv_prepare_irq_remapping()
165 * into ioapic_max_cpumask if its APIC ID is less than 256. in hyperv_prepare_irq_remapping()
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| /linux-6.14.4/Documentation/arch/x86/i386/ |
| D | IO-APIC.rst | 4 IO-APIC
9 Most (all) Intel-MP compliant SMP boards have the so-called 'IO-APIC',
12 IO-APIC, interrupts from hardware will be delivered only to the
23 If your box boots fine with enabled IO-APIC IRQs, then your
28 0: 1360293 IO-APIC-edge timer
29 1: 4 IO-APIC-edge keyboard
32 14: 1448 IO-APIC-edge ide0
33 16: 28232 IO-APIC-level Intel EtherExpress Pro 10/100 Ethernet
34 17: 51304 IO-APIC-level eth0
97 board does not do default daisy-chaining. (or the IO-APIC has the PIRQ pins
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| /linux-6.14.4/arch/x86/kernel/ |
| D | irqinit.c | 27 #include <asm/apic.h>
35 * ISA PIC or low IO-APIC triggered (INTA-cycle or APIC) interrupts:
40 * The IO-APIC gives us many more interrupt sources. Most of these
45 * IO-APIC registers.
60 * Try to set up the through-local-APIC virtual wire mode earlier. in init_ISA_irqs()
62 * On some 32-bit UP machines, whose APIC has been disabled by BIOS in init_ISA_irqs()
83 * these IRQs are handled by more modern controllers like IO-APIC, in init_IRQ()
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| D | smpboot.c | 26 * Ingo Molnar : Added APIC timers, based on code
77 #include <asm/apic.h>
184 * point before an INIT_deassert IPI reaches the local APIC, so it in ap_starting()
185 * is now safe to touch the local APIC. in ap_starting()
187 * Set up this CPU, first the APIC, which is probably redundant on in ap_starting()
696 /* Be paranoid about clearing APIC errors. */ in send_init_sequence()
732 * Determine this based on the APIC version. in wakeup_secondary_cpu_via_init()
733 * If we don't have an integrated APIC, don't send the STARTUP IPIs. in wakeup_secondary_cpu_via_init()
792 pr_err("APIC never delivered???\n"); in wakeup_secondary_cpu_via_init()
794 pr_err("APIC delivery error (%lx)\n", accept_status); in wakeup_secondary_cpu_via_init()
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| /linux-6.14.4/arch/x86/kvm/svm/ |
| D | avic.c | 31 * Encode the arbitrary VM ID and the vCPU's default APIC ID, i.e the vCPU ID,
36 * guest physical APIC ID (limited by the size of the physical ID table), and
97 * achieved using AVIC doorbell. KVM disables the APIC access page in avic_activate_vmcb()
101 if (x2avic_enabled && apic_x2apic_mode(svm->vcpu.arch.apic)) { in avic_activate_vmcb()
108 * Flush the TLB, the guest may have inserted a non-APIC in avic_activate_vmcb()
205 /* Allocating physical APIC ID table (4KB) */ in avic_vm_init()
212 /* Allocating logical APIC ID table (4KB) */ in avic_vm_init()
287 if (!vcpu->arch.apic->regs) in avic_init_backing_page()
304 svm->avic_backing_page = virt_to_page(vcpu->arch.apic->regs); in avic_init_backing_page()
306 /* Setting AVIC backing page address in the phy APIC ID table */ in avic_init_backing_page()
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| /linux-6.14.4/Documentation/virt/kvm/x86/ |
| D | hypercalls.rst | 99 specifying APIC ID (a1) of the vcpu to be woken up. An additional argument (a0)
147 - a0: lower part of the bitmap of destination APIC IDs
148 - a1: higher part of the bitmap of destination APIC IDs
149 - a2: the lowest APIC ID in bitmap
150 - a3: APIC ICR
156 a0 corresponds to the APIC ID in the third argument (a2), bit 1
157 corresponds to the APIC ID a2+1, and so on.
168 a0: destination APIC ID
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