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/linux-6.14.4/Documentation/devicetree/bindings/mtd/
Dcdns,hp-nfc.yaml1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Niravkumar L Rabara <[email protected]>
13 - $ref: nand-controller.yaml
18 - const: cdns,hp-nfc
22 - description: Controller register set
23 - description: Slave DMA data port register set
25 reg-names:
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/memory-controllers/
Dmvebu-devbus.txt9 - compatible: Armada 370/XP SoC are supported using the
10 "marvell,mvebu-devbus" compatible string.
13 "marvell,orion-devbus" compatible string.
15 - reg: A resource specifier for the register space.
20 - #address-cells: Must be set to 1
21 - #size-cells: Must be set to 1
22 - ranges: Must be set up to reflect the memory layout with four
23 integer values for each chip-select line in use:
28 - devbus,keep-config This property can optionally be used to keep
37 - devbus,turn-off-ps: Defines the time during which the controller does not
[all …]
/linux-6.14.4/Documentation/devicetree/bindings/net/
Dapm-xgene-enet.txt1 APM X-Gene SoC Ethernet nodes
3 Ethernet nodes are defined to describe on-chip ethernet interfaces in
4 APM X-Gene SoC.
7 - compatible: Should state binding information from the following list,
8 - "apm,xgene-enet": RGMII based 1G interface
9 - "apm,xgene1-sgenet": SGMII based 1G interface
10 - "apm,xgene1-xgenet": XFI based 10G interface
11 - reg: Address and length of the register set for the device. It contains the
12 information of registers in the same order as described by reg-names
13 - reg-names: Should contain the register set names
[all …]
Drenesas,etheravb.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Sergei Shtylyov <[email protected]>
15 - items:
16 - enum:
17 - renesas,etheravb-r8a7742 # RZ/G1H
18 - renesas,etheravb-r8a7743 # RZ/G1M
19 - renesas,etheravb-r8a7744 # RZ/G1N
20 - renesas,etheravb-r8a7745 # RZ/G1E
[all …]
Dfsl,fec.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Shawn Guo <[email protected]>
11 - Wei Fang <[email protected]>
12 - NXP Linux Team <linux-[email protected]>
15 - $ref: ethernet-controller.yaml#
20 - enum:
21 - fsl,imx25-fec
22 - fsl,imx27-fec
[all …]
Dethernet-phy.yaml1 # SPDX-License-Identifier: GPL-2.0
3 ---
4 $id: http://devicetree.org/schemas/net/ethernet-phy.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
10 - Andrew Lunn <[email protected]>
11 - Florian Fainelli <[email protected]>
12 - Heiner Kallweit <[email protected]>
14 # The dt-schema tools will generate a select statement first by using
21 pattern: "^ethernet-phy(@[a-f0-9]+)?$"
24 - $nodename
[all …]
/linux-6.14.4/arch/arm/boot/dts/intel/socfpga/
Dsocfpga_cyclone5_sodia.dts1 // SPDX-License-Identifier: GPL-2.0+
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
11 model = "Altera SOCFPGA Cyclone V SoC Macnica Sodia board";
12 compatible = "macnica,sodia", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
30 compatible = "regulator-fixed";
31 regulator-name = "3.3V";
32 regulator-min-microvolt = <3300000>;
33 regulator-max-microvolt = <3300000>;
[all …]
Dsocfpga_cyclone5_vining_fpga.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR X11)
7 #include <dt-bindings/gpio/gpio.h>
8 #include <dt-bindings/input/input.h>
12 compatible = "samtec,vining", "altr,socfpga-cyclone5", "altr,socfpga";
16 stdout-path = "serial0:115200n8";
34 gpio-keys {
35 compatible = "gpio-keys";
68 regulator-usb-nrst {
69 compatible = "regulator-fixed";
70 regulator-name = "usb_nrst";
[all …]
/linux-6.14.4/arch/arm64/boot/dts/renesas/
Dhihope-rzg2-ex.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the RZ/G2[HMN] HiHope sub board common parts
19 pinctrl-0 = <&avb_pins>;
20 pinctrl-names = "default";
21 phy-handle = <&phy0>;
22 tx-internal-delay-ps = <2000>;
23 rx-internal-delay-ps = <1800>;
26 phy0: ethernet-phy@0 {
27 compatible = "ethernet-phy-id001c.c915",
28 "ethernet-phy-ieee802.3-c22";
[all …]
Dr8a77970-v3msk.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the V3M Starter Kit board
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
14 model = "Renesas V3M Starter Kit board";
27 stdout-path = "serial0:115200n8";
30 hdmi-out {
31 compatible = "hdmi-connector";
36 remote-endpoint = <&adv7511_out>;
41 lvds-decoder {
[all …]
Dr8a779a0-falcon.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Falcon CPU and BreakOut boards with R-Car V3U
8 /dts-v1/;
9 #include "r8a779a0-falcon-cpu.dtsi"
10 #include "r8a779a0-falcon-csi-dsi.dtsi"
11 #include "r8a779a0-falcon-ethernet.dtsi"
15 compatible = "renesas,falcon-breakout", "renesas,falcon-cpu", "renesas,r8a779a0";
23 pinctrl-0 = <&avb0_pins>;
24 pinctrl-names = "default";
25 phy-handle = <&phy0>;
[all …]
Dr8a77970-eagle.dts1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the Eagle board with R-Car V3M
5 * Copyright (C) 2016-2017 Renesas Electronics Corp.
9 /dts-v1/;
11 #include <dt-bindings/gpio/gpio.h>
14 model = "Renesas Eagle board based on r8a77970";
29 stdout-path = "serial0:115200n8";
32 d1p8: regulator-fixed {
33 compatible = "regulator-fixed";
34 regulator-name = "fixed-1.8V";
[all …]
Dulcb.dtsi1 // SPDX-License-Identifier: GPL-2.0
3 * Device Tree Source for the R-Car Gen3 ULCB board
14 #include <dt-bindings/gpio/gpio.h>
15 #include <dt-bindings/input/input.h>
18 model = "Renesas R-Car Gen3 ULCB board";
37 stdout-path = "serial0:115200n8";
40 audio_clkout: audio-clkout {
43 * but needed to avoid cs2000/rcar_sound probe dead-lock
45 compatible = "fixed-clock";
46 #clock-cells = <0>;
[all …]
Dr8a779h0-gray-hawk-single.dts1 // SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 * Device Tree Source for the R-Car V4M Gray Hawk Single board
11 * Because R-Car V4M has only 1 SSI, it cannot handle both Playback/Capture
28 /dts-v1/;
30 #include <dt-bindings/gpio/gpio.h>
31 #include <dt-bindings/input/input.h>
32 #include <dt-bindings/leds/common.h>
33 #include <dt-bindings/media/video-interfaces.h>
38 model = "Renesas Gray Hawk Single board based on r8a779h0";
39 compatible = "renesas,gray-hawk-single", "renesas,r8a779h0";
[all …]
/linux-6.14.4/arch/arm64/boot/dts/allwinner/
Dsun50i-h618-longanpi-3h.dts1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
6 /dts-v1/;
8 #include "sun50i-h618-longan-module-3h.dtsi"
10 #include <dt-bindings/gpio/gpio.h>
11 #include <dt-bindings/interrupt-controller/arm-gic.h>
12 #include <dt-bindings/leds/common.h>
16 compatible = "sipeed,longan-pi-3h", "sipeed,longan-module-3h", "allwinner,sun50i-h618";
24 stdout-path = "serial0:115200n8";
28 compatible = "gpio-leds";
30 led-0 {
[all …]
/linux-6.14.4/arch/riscv/boot/dts/starfive/
Djh7100-starfive-visionfive-v1.dts1 // SPDX-License-Identifier: GPL-2.0 OR MIT
7 /dts-v1/;
8 #include "jh7100-common.dtsi"
12 compatible = "starfive,visionfive-v1", "starfive,jh7100";
14 gpio-restart {
15 compatible = "gpio-restart";
22 phy-handle = <&phy>;
26 * The board uses a Motorcomm YT8521 PHY supporting RGMII-ID, but requires
27 * manual adjustment of the RX internal delay to work properly. The default
28 * RX delay provided by the driver (1.95ns) is too high, but applying a 50%
[all …]
/linux-6.14.4/drivers/mmc/host/
Ddw_mmc-rockchip.c1 // SPDX-License-Identifier: GPL-2.0-or-later
11 #include <linux/mmc/slot-gpio.h>
16 #include "dw_mmc-pltfm.h"
41 * Each fine delay is between 44ps-77ps. Assume each fine delay is 60ps to
46 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_get_internal_phase()
78 struct dw_mci_rockchip_priv_data *priv = host->priv; in rockchip_mmc_get_phase()
79 struct clk *clock = sample ? priv->sample_clk : priv->drv_clk; in rockchip_mmc_get_phase()
81 if (priv->internal_phase) in rockchip_mmc_get_phase()
89 unsigned long rate = clk_get_rate(host->ciu_clk); in rockchip_mmc_set_internal_phase()
93 u32 delay; in rockchip_mmc_set_internal_phase() local
[all …]
/linux-6.14.4/arch/arm/boot/dts/marvell/
Darmada-385-atl-x530.dts1 // SPDX-License-Identifier: (GPL-2.0 OR MIT)
3 * Device Tree file for Armada 385 Allied Telesis x530/GS980MX Board.
4 (x530/AT-GS980MX)
9 /dts-v1/;
10 #include "armada-385.dtsi"
12 #include <dt-bindings/gpio/gpio.h>
15 model = "x530/AT-GS980MX";
19 stdout-path = "serial1:115200n8";
32 internal-regs {
34 pinctrl-names = "default";
[all …]
/linux-6.14.4/include/linux/platform_data/
Dpxa_sdhci.h1 /* SPDX-License-Identifier: GPL-2.0-only */
8 * PXA Platform - SDHCI platform data definitions
17 /* card always wired to host, like on-chip emmc */
19 /* Board design supports 8-bit data on SD/SDIO BUS */
23 * struct pxa_sdhci_platdata() - Platform device data for PXA SDHCI
26 * mmp2: each step is roughly 100ps, 5bits width
30 * 1: choose feedback clk + delay value
/linux-6.14.4/arch/arm/boot/dts/nxp/ls/
Dls1021a-tsn.dts1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright 2016-2018 NXP Semiconductors
6 /dts-v1/;
10 model = "NXP LS1021A-TSN Board";
11 compatible = "fsl,ls1021a-tsn", "fsl,ls1021a";
13 sys_mclk: clock-mclk {
14 compatible = "fixed-clock";
15 #clock-cells = <0>;
16 clock-frequency = <24576000>;
19 reg_vdda_codec: regulator-3V3 {
[all …]
/linux-6.14.4/arch/arm/boot/dts/ti/omap/
Domap2420-n8x0-common.dtsi1 // SPDX-License-Identifier: GPL-2.0
11 stdout-path = &uart3;
16 compatible = "i2c-cbus-gpio";
21 #address-cells = <1>;
22 #size-cells = <0>;
25 interrupt-parent = <&gpio4>;
34 clock-frequency = <400000>;
44 clock-frequency = <400000>;
50 /* gpio-irq for dma: 26 */
53 #address-cells = <1>;
[all …]
Domap3-overo-base.dtsi1 // SPDX-License-Identifier: GPL-2.0-only
7 * The Gumstix Overo must be combined with an expansion board.
17 led-controller {
18 compatible = "pwm-leds";
20 led-1 {
23 max-brightness = <127>;
24 linux,default-trigger = "mmc0";
29 compatible = "ti,omap-twl4030";
37 compatible = "regulator-fixed";
38 regulator-name = "hsusb2_vbus";
[all …]
Dam3874-iceboard.dts1 // SPDX-License-Identifier: GPL-2.0
8 * This is an ARM + FPGA instrumentation board used at telescopes in
12 * Copyright (c) 2019 Three-Speed Logic, Inc. <[email protected]>
15 /dts-v1/;
18 #include <dt-bindings/interrupt-controller/irq.h>
25 stdout-path = "serial1:115200n8";
35 compatible = "regulator-fixed";
36 regulator-name = "vmmcsd_fixed";
37 regulator-min-microvolt = <3300000>;
38 regulator-max-microvolt = <3300000>;
[all …]
/linux-6.14.4/arch/arm/boot/dts/allwinner/
Dsun8i-a83t-bananapi-m3.dts2 * Copyright 2017 Chen-Yu Tsai
4 * Chen-Yu Tsai <[email protected]>
6 * This file is dual-licensed: you can use it either under the terms
45 /dts-v1/;
46 #include "sun8i-a83t.dtsi"
48 #include <dt-bindings/gpio/gpio.h>
51 model = "Banana Pi BPI-M3";
52 compatible = "sinovoip,bpi-m3", "allwinner,sun8i-a83t";
60 stdout-path = "serial0:115200n8";
64 compatible = "hdmi-connector";
[all …]
/linux-6.14.4/arch/arm/boot/dts/nxp/imx/
Dimx6qp-prtwd3.dts1 // SPDX-License-Identifier: GPL-2.0-or-later OR MIT
7 /dts-v1/;
8 #include <dt-bindings/gpio/gpio.h>
12 model = "Protonic WD3 board";
16 stdout-path = &uart4;
29 clock_ksz8081: clock-ksz8081 {
30 compatible = "fixed-clock";
31 #clock-cells = <0>;
32 clock-frequency = <50000000>;
35 clock_ksz9031: clock-ksz9031 {
[all …]

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