1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/mtd/cdns,hp-nfc.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Cadence NAND controller
8
9maintainers:
10  - Niravkumar L Rabara <[email protected]>
11
12allOf:
13  - $ref: nand-controller.yaml
14
15properties:
16  compatible:
17    items:
18      - const: cdns,hp-nfc
19
20  reg:
21    items:
22      - description: Controller register set
23      - description: Slave DMA data port register set
24
25  reg-names:
26    items:
27      - const: reg
28      - const: sdma
29
30  interrupts:
31    maxItems: 1
32
33  clocks:
34    maxItems: 1
35
36  clock-names:
37    items:
38      - const: nf_clk
39
40  dmas:
41    maxItems: 1
42
43  cdns,board-delay-ps:
44    description: |
45      Estimated Board delay. The value includes the total round trip
46      delay for the signals and is used for deciding on values associated
47      with data read capture. The example formula for SDR mode is the
48      following.
49      board delay = RE#PAD delay + PCB trace to device + PCB trace from device
50      + DQ PAD delay
51
52required:
53  - compatible
54  - reg
55  - reg-names
56  - interrupts
57  - clocks
58  - clock-names
59
60unevaluatedProperties: false
61
62examples:
63  - |
64    #include <dt-bindings/interrupt-controller/arm-gic.h>
65
66    nand-controller@10b80000 {
67        compatible = "cdns,hp-nfc";
68        reg = <0x10b80000 0x10000>,
69              <0x10840000 0x10000>;
70        reg-names = "reg", "sdma";
71        #address-cells = <1>;
72        #size-cells = <0>;
73        interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
74        clocks = <&clk>;
75        clock-names = "nf_clk";
76        cdns,board-delay-ps = <4830>;
77
78        nand@0 {
79            reg = <0>;
80        };
81    };
82