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/aosp_15_r20/external/llvm/test/CodeGen/X86/
H A Dlarge-gep-chain.ll4 %0 = type { i32, float* }
24 %tmp = getelementptr inbounds float, float* null, i64 1
25 %tmp3 = getelementptr inbounds float, float* %tmp, i64 1
26 %tmp4 = getelementptr inbounds float, float* %tmp3, i64 1
27 %tmp5 = getelementptr inbounds float, float* %tmp4, i64 1
28 %tmp6 = getelementptr inbounds float, float* %tmp5, i64 1
29 %tmp7 = getelementptr inbounds float, float* %tmp6, i64 1
30 %tmp8 = getelementptr inbounds float, float* %tmp7, i64 1
31 %tmp9 = getelementptr inbounds float, float* %tmp8, i64 1
32 %tmp10 = getelementptr inbounds float, float* %tmp9, i64 1
[all …]
H A D2008-07-19-movups-spills.ll7 @0 = external global <4 x float>, align 1 ; <<4 x float>*>:0 [#uses=2]
8 @1 = external global <4 x float>, align 1 ; <<4 x float>*>:1 [#uses=1]
9 @2 = external global <4 x float>, align 1 ; <<4 x float>*>:2 [#uses=1]
10 @3 = external global <4 x float>, align 1 ; <<4 x float>*>:3 [#uses=1]
11 @4 = external global <4 x float>, align 1 ; <<4 x float>*>:4 [#uses=1]
12 @5 = external global <4 x float>, align 1 ; <<4 x float>*>:5 [#uses=1]
13 @6 = external global <4 x float>, align 1 ; <<4 x float>*>:6 [#uses=1]
14 @7 = external global <4 x float>, align 1 ; <<4 x float>*>:7 [#uses=1]
15 @8 = external global <4 x float>, align 1 ; <<4 x float>*>:8 [#uses=1]
16 @9 = external global <4 x float>, align 1 ; <<4 x float>*>:9 [#uses=1]
[all …]
/aosp_15_r20/external/llvm/test/CodeGen/AMDGPU/
H A Dbig_alu.ll5 …float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 …
7 %tmp = extractelement <4 x float> %reg0, i32 0
8 %tmp1 = extractelement <4 x float> %reg0, i32 1
9 %tmp2 = extractelement <4 x float> %reg0, i32 2
10 %tmp3 = extractelement <4 x float> %reg0, i32 3
11 %tmp4 = extractelement <4 x float> %reg1, i32 0
12 %tmp5 = extractelement <4 x float> %reg9, i32 0
13 %tmp6 = extractelement <4 x float> %reg8, i32 0
14 %tmp7 = fcmp ugt float %tmp6, 0.000000e+00
15 %tmp8 = select i1 %tmp7, float %tmp4, float %tmp5
[all …]
H A Dvgpr-spill-emergency-stack-slot-compute.ll46 …void @spill_vgpr_compute(<4 x float> %arg6, float addrspace(1)* %arg, i32 %arg1, i32 %arg2, float …
49 %tmp7 = extractelement <4 x float> %arg6, i32 0
50 %tmp8 = extractelement <4 x float> %arg6, i32 1
51 %tmp9 = extractelement <4 x float> %arg6, i32 2
52 %tmp10 = extractelement <4 x float> %arg6, i32 3
53 %tmp11 = bitcast float %arg5 to i32
57 %tmp13 = phi float [ 0.000000e+00, %bb ], [ %tmp338, %bb145 ]
58 %tmp14 = phi float [ 0.000000e+00, %bb ], [ %tmp337, %bb145 ]
59 %tmp15 = phi float [ 0.000000e+00, %bb ], [ %tmp336, %bb145 ]
60 %tmp16 = phi float [ 0.000000e+00, %bb ], [ %tmp339, %bb145 ]
[all …]
H A Dvgpr-spill-emergency-stack-slot.ll33 %tmp12 = call float @llvm.SI.load.const(<16 x i8> %tmp11, i32 0)
34 %tmp13 = call float @llvm.SI.load.const(<16 x i8> %tmp11, i32 16)
35 %tmp14 = call float @llvm.SI.load.const(<16 x i8> %tmp11, i32 32)
39 %tmp18 = call <4 x float> @llvm.SI.vs.load.input(<16 x i8> %tmp16, i32 0, i32 %tmp17)
40 %tmp19 = extractelement <4 x float> %tmp18, i32 0
41 %tmp20 = extractelement <4 x float> %tmp18, i32 1
42 %tmp21 = extractelement <4 x float> %tmp18, i32 2
43 %tmp22 = extractelement <4 x float> %tmp18, i32 3
44 %tmp23 = bitcast float %tmp14 to i32
48 %tmp25 = phi float [ 0.000000e+00, %bb ], [ %tmp350, %bb157 ]
[all …]
H A Dsi-sgpr-spill.ll25 …float inreg %arg3, i32 inreg %arg4, <2 x i32> %arg5, <2 x i32> %arg6, <2 x i32> %arg7, <3 x i32> %…
29 %tmp22 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 96)
30 %tmp23 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 100)
31 %tmp24 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 104)
32 %tmp25 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 112)
33 %tmp26 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 116)
34 %tmp27 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 120)
35 %tmp28 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 128)
36 %tmp29 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 132)
37 %tmp30 = call float @llvm.SI.load.const(<16 x i8> %tmp21, i32 140)
[all …]
H A Dsi-spill-cf.ll11 %0 = call float @llvm.SI.load.const(<16 x i8> undef, i32 16)
12 %1 = call float @llvm.SI.load.const(<16 x i8> undef, i32 32)
13 %2 = call float @llvm.SI.load.const(<16 x i8> undef, i32 80)
14 %3 = call float @llvm.SI.load.const(<16 x i8> undef, i32 84)
15 %4 = call float @llvm.SI.load.const(<16 x i8> undef, i32 88)
16 %5 = call float @llvm.SI.load.const(<16 x i8> undef, i32 96)
17 %6 = call float @llvm.SI.load.const(<16 x i8> undef, i32 100)
18 %7 = call float @llvm.SI.load.const(<16 x i8> undef, i32 104)
19 %8 = call float @llvm.SI.load.const(<16 x i8> undef, i32 112)
20 %9 = call float @llvm.SI.load.const(<16 x i8> undef, i32 116)
[all …]
H A Dpv.ll6 …float> inreg %reg0, <4 x float> inreg %reg1, <4 x float> inreg %reg2, <4 x float> inreg %reg3, <4 …
8 %0 = extractelement <4 x float> %reg1, i32 0
9 %1 = extractelement <4 x float> %reg1, i32 1
10 %2 = extractelement <4 x float> %reg1, i32 2
11 %3 = extractelement <4 x float> %reg1, i32 3
12 %4 = extractelement <4 x float> %reg2, i32 0
13 %5 = extractelement <4 x float> %reg2, i32 1
14 %6 = extractelement <4 x float> %reg2, i32 2
15 %7 = extractelement <4 x float> %reg2, i32 3
16 %8 = extractelement <4 x float> %reg3, i32 0
[all …]
/aosp_15_r20/external/llvm/test/Transforms/InstCombine/
H A Dx86-sse.ll5 define float @test_rcp_ss_0(float %a) {
7 ; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x float> undef, float %a, i32 0
8 ; CHECK-NEXT: [[TMP2:%.*]] = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> [[TMP1]])
9 ; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x float> [[TMP2]], i32 0
10 ; CHECK-NEXT: ret float [[TMP3]]
12 %1 = insertelement <4 x float> undef, float %a, i32 0
13 %2 = insertelement <4 x float> %1, float 1.000000e+00, i32 1
14 %3 = insertelement <4 x float> %2, float 2.000000e+00, i32 2
15 %4 = insertelement <4 x float> %3, float 3.000000e+00, i32 3
16 %5 = tail call <4 x float> @llvm.x86.sse.rcp.ss(<4 x float> %4)
[all …]
/aosp_15_r20/external/llvm/test/Transforms/SLPVectorizer/X86/
H A Dfma.ll13 @srcA32 = common global [16 x float] zeroinitializer, align 64
14 @srcB32 = common global [16 x float] zeroinitializer, align 64
15 @srcC32 = common global [16 x float] zeroinitializer, align 64
17 @dst32 = common global [16 x float] zeroinitializer, align 64
19 declare float @llvm.fma.f32(float, float, float)
226 ; NO-FMA-NEXT: [[A0:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float…
227 ; NO-FMA-NEXT: [[A1:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float…
228 ; NO-FMA-NEXT: [[A2:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float…
229 ; NO-FMA-NEXT: [[A3:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float…
230 ; NO-FMA-NEXT: [[B0:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float…
[all …]
H A Dfround.ll12 @src32 = common global [16 x float] zeroinitializer, align 64
13 @dst32 = common global [16 x float] zeroinitializer, align 64
21 declare float @llvm.ceil.f32(float %p)
22 declare float @llvm.floor.f32(float %p)
23 declare float @llvm.nearbyint.f32(float %p)
24 declare float @llvm.rint.f32(float %p)
25 declare float @llvm.trunc.f32(float %p)
884 ; SSE2-NEXT: [[LD0:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]…
885 ; SSE2-NEXT: [[LD1:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]…
886 ; SSE2-NEXT: [[LD2:%.*]] = load float, float* getelementptr inbounds ([16 x float], [16 x float]…
[all …]
/aosp_15_r20/external/llvm/test/CodeGen/Generic/
H A D2003-05-28-ManyArgs.ll21 %struct..s_annealing_sched = type { i32, float, float, float, float }
22 %struct..s_chan = type { i32, float, float, float, float }
23 …%struct..s_det_routing_arch = type { i32, float, float, float, i32, i32, i16, i16, i16, float, flo…
24 %struct..s_placer_opts = type { i32, float, i32, i32, i8*, i32, i32 }
25 %struct..s_router_opts = type { float, float, float, float, float, i32, i32, i32, i32 }
26 %struct..s_segment_inf = type { float, i32, i16, i16, float, float, i32, float, float }
27 %struct..s_switch_inf = type { i32, float, float, float, float }
44 … float, float, float, float, float, float, float, float, float, float } ; <{ i32, float, float, f…
50 …2, float, float, float, float, float, float, float, float, float, float }, { i32, float, float, fl…
56 …tr %struct..s_placer_opts, %struct..s_placer_opts* %placer_opts, i64 0, i32 1 ; <float*> [#uses=1]
[all …]
/aosp_15_r20/external/llvm/test/Transforms/LoopReroll/
H A Dbasic32iters.ll5 ; void goo32(float alpha, float *a, float *b) {
43 define void @goo32(float %alpha, float* %a, float* readonly %b) #0 {
49 %arrayidx = getelementptr inbounds float, float* %b, i64 %indvars.iv
50 %0 = load float, float* %arrayidx, align 4
51 %mul = fmul float %0, %alpha
52 %arrayidx2 = getelementptr inbounds float, float* %a, i64 %indvars.iv
53 %1 = load float, float* %arrayidx2, align 4
54 %add = fadd float %1, %mul
55 store float %add, float* %arrayidx2, align 4
57 %arrayidx5 = getelementptr inbounds float, float* %b, i64 %2
[all …]
/aosp_15_r20/external/deqp/data/gles3/shaders/
H A Dqualification_order.test14 precision mediump float;
17 invariant smooth centroid out lowp float x0;
19 flat out mediump float x1;
21 uniform highp float x2;
33 precision mediump float;
36 smooth centroid in lowp float x0;
38 flat in mediump float x1;
40 uniform highp float x2;
44 float result = (x0 + x1 + x2) / 3.0;
55 precision mediump float;
[all …]
/aosp_15_r20/external/deqp-deps/glslang/Test/baseResults/
Dhlsl.intrinsics.vert.out4 0:2 Function Definition: VertexShaderFunctionS(f1;f1;f1;u1;u1; ( temp float)
6 0:2 'inF0' ( in float)
7 0:2 'inF1' ( in float)
8 0:2 'inF2' ( in float)
13 0:3 Convert float to bool ( temp bool)
14 0:3 'inF0' ( in float)
15 0:4 Absolute value ( temp float)
16 0:4 'inF0' ( in float)
17 0:5 arc cosine ( temp float)
18 0:5 'inF0' ( in float)
[all …]
Dhlsl.intrinsics.frag.out5 0:17 Function Definition: PixelShaderFunctionS(f1;f1;f1;u1;i1; ( temp float)
7 0:17 'inF0' ( in float)
8 0:17 'inF1' ( in float)
9 0:17 'inF2' ( in float)
17 0:20 Convert float to bool ( temp bool)
18 0:20 'inF0' ( in float)
20 0:21 move second child to first child ( temp float)
21 0:21 'r001' ( temp float)
22 0:21 Absolute value ( temp float)
23 0:21 'inF0' ( in float)
[all …]
/aosp_15_r20/external/angle/third_party/glslang/src/Test/baseResults/
H A Dhlsl.intrinsics.vert.out4 0:2 Function Definition: VertexShaderFunctionS(f1;f1;f1;u1;u1; ( temp float)
6 0:2 'inF0' ( in float)
7 0:2 'inF1' ( in float)
8 0:2 'inF2' ( in float)
13 0:3 Convert float to bool ( temp bool)
14 0:3 'inF0' ( in float)
15 0:4 Absolute value ( temp float)
16 0:4 'inF0' ( in float)
17 0:5 arc cosine ( temp float)
18 0:5 'inF0' ( in float)
[all …]
H A Dhlsl.intrinsics.frag.out5 0:17 Function Definition: PixelShaderFunctionS(f1;f1;f1;u1;i1; ( temp float)
7 0:17 'inF0' ( in float)
8 0:17 'inF1' ( in float)
9 0:17 'inF2' ( in float)
17 0:20 Convert float to bool ( temp bool)
18 0:20 'inF0' ( in float)
20 0:21 move second child to first child ( temp float)
21 0:21 'r001' ( temp float)
22 0:21 Absolute value ( temp float)
23 0:21 'inF0' ( in float)
[all …]
/aosp_15_r20/external/llvm/test/CodeGen/PowerPC/
H A D2007-03-30-SpillerCrash.ll3 define void @test(<4 x float>*, { { i16, i16, i32 } }*) {
6 …getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 175, i32 3 ;…
7 …getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 174, i32 2 ;…
8 …getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 174, i32 3 ;…
9 …getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 1 ;…
10 …getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 2 ;…
11 …getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 173, i32 3 ;…
12 …getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 1 ;…
13 …getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 2 ;…
14 …getelementptr [193 x [4 x <4 x float>]], [193 x [4 x <4 x float>]]* null, i32 0, i32 172, i32 3 ;…
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567/lib/clang/19/include/
D__clang_cuda_libdevice_declares.h26 __DEVICE__ float __nv_acosf(float __a);
28 __DEVICE__ float __nv_acoshf(float __a);
30 __DEVICE__ float __nv_asinf(float __a);
32 __DEVICE__ float __nv_asinhf(float __a);
34 __DEVICE__ float __nv_atan2f(float __a, float __b);
36 __DEVICE__ float __nv_atanf(float __a);
38 __DEVICE__ float __nv_atanhf(float __a);
43 __DEVICE__ float __nv_cbrtf(float __a);
45 __DEVICE__ float __nv_ceilf(float __a);
49 __DEVICE__ float __nv_copysignf(float __a, float __b);
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r522817/lib/clang/18/include/
D__clang_cuda_libdevice_declares.h26 __DEVICE__ float __nv_acosf(float __a);
28 __DEVICE__ float __nv_acoshf(float __a);
30 __DEVICE__ float __nv_asinf(float __a);
32 __DEVICE__ float __nv_asinhf(float __a);
34 __DEVICE__ float __nv_atan2f(float __a, float __b);
36 __DEVICE__ float __nv_atanf(float __a);
38 __DEVICE__ float __nv_atanhf(float __a);
43 __DEVICE__ float __nv_cbrtf(float __a);
45 __DEVICE__ float __nv_ceilf(float __a);
49 __DEVICE__ float __nv_copysignf(float __a, float __b);
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r530567b/lib/clang/19/include/
D__clang_cuda_libdevice_declares.h26 __DEVICE__ float __nv_acosf(float __a);
28 __DEVICE__ float __nv_acoshf(float __a);
30 __DEVICE__ float __nv_asinf(float __a);
32 __DEVICE__ float __nv_asinhf(float __a);
34 __DEVICE__ float __nv_atan2f(float __a, float __b);
36 __DEVICE__ float __nv_atanf(float __a);
38 __DEVICE__ float __nv_atanhf(float __a);
43 __DEVICE__ float __nv_cbrtf(float __a);
45 __DEVICE__ float __nv_ceilf(float __a);
49 __DEVICE__ float __nv_copysignf(float __a, float __b);
[all …]
/aosp_15_r20/prebuilts/clang-tools/linux-x86/lib64/clang/19/include/
H A D__clang_cuda_libdevice_declares.h26 __DEVICE__ float __nv_acosf(float __a);
28 __DEVICE__ float __nv_acoshf(float __a);
30 __DEVICE__ float __nv_asinf(float __a);
32 __DEVICE__ float __nv_asinhf(float __a);
34 __DEVICE__ float __nv_atan2f(float __a, float __b);
36 __DEVICE__ float __nv_atanf(float __a);
38 __DEVICE__ float __nv_atanhf(float __a);
43 __DEVICE__ float __nv_cbrtf(float __a);
45 __DEVICE__ float __nv_ceilf(float __a);
49 __DEVICE__ float __nv_copysignf(float __a, float __b);
[all …]
/aosp_15_r20/prebuilts/clang/host/linux-x86/clang-r536225/lib/clang/19/include/
D__clang_cuda_libdevice_declares.h26 __DEVICE__ float __nv_acosf(float __a);
28 __DEVICE__ float __nv_acoshf(float __a);
30 __DEVICE__ float __nv_asinf(float __a);
32 __DEVICE__ float __nv_asinhf(float __a);
34 __DEVICE__ float __nv_atan2f(float __a, float __b);
36 __DEVICE__ float __nv_atanf(float __a);
38 __DEVICE__ float __nv_atanhf(float __a);
43 __DEVICE__ float __nv_cbrtf(float __a);
45 __DEVICE__ float __nv_ceilf(float __a);
49 __DEVICE__ float __nv_copysignf(float __a, float __b);
[all …]
/aosp_15_r20/external/XNNPACK/src/xnnpack/
H A Dmicroparams.h50 XNN_ALIGN(32) float scale[8];
51 XNN_ALIGN(32) float min[8];
52 XNN_ALIGN(32) float max[8];
59 float scale;
60 float min;
61 float max;
65 XNN_ALIGN(16) float scale[4];
66 XNN_ALIGN(16) float min[4];
67 XNN_ALIGN(16) float max[4];
77 float min;
[all …]

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