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/linux-6.14.4/Documentation/devicetree/bindings/crypto/
Dqcom,inline-crypto-engine.yaml1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/crypto/qcom,inline-crypto-engine.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. (QTI) Inline Crypto Engine
10 - Bjorn Andersson <[email protected]>
15 - enum:
16 - qcom,qcs8300-inline-crypto-engine
17 - qcom,sa8775p-inline-crypto-engine
18 - qcom,sc7180-inline-crypto-engine
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/linux-6.14.4/drivers/crypto/marvell/cesa/
Dcesa.h1 /* SPDX-License-Identifier: GPL-2.0 */
5 #include <crypto/internal/hash.h>
6 #include <crypto/internal/skcipher.h>
8 #include <linux/dma-direction.h>
70 * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
124 * /-----------\ 0
126 * |-----------| 0x20
128 * |-----------| 0x40
130 * |-----------| 0x40 (inplace)
132 * |-----------| 0x80
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Dcesa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Support for Marvell's Cryptographic Engine and Security Accelerator (CESA)
5 * driver supports the TDMA engine on platforms on which it is available.
7 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
15 #include <linux/dma-mapping.h>
32 /* Limit of the crypto queue before reaching the backlog */
38 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine, in mv_cesa_dequeue_req_locked() argument
43 *backlog = crypto_get_backlog(&engine->queue); in mv_cesa_dequeue_req_locked()
44 req = crypto_dequeue_request(&engine->queue); in mv_cesa_dequeue_req_locked()
52 static void mv_cesa_rearm_engine(struct mv_cesa_engine *engine) in mv_cesa_rearm_engine() argument
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Dcipher.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
12 #include <crypto/aes.h>
13 #include <crypto/internal/des.h>
15 #include <linux/dma-mapping.h>
40 static inline void
44 mv_cesa_req_dma_iter_init(&iter->base, req->cryptlen); in mv_cesa_skcipher_req_iter_init()
45 mv_cesa_sg_dma_iter_init(&iter->src, req->src, DMA_TO_DEVICE); in mv_cesa_skcipher_req_iter_init()
46 mv_cesa_sg_dma_iter_init(&iter->dst, req->dst, DMA_FROM_DEVICE); in mv_cesa_skcipher_req_iter_init()
49 static inline bool
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Dhash.c1 // SPDX-License-Identifier: GPL-2.0-only
5 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
12 #include <crypto/hmac.h>
13 #include <crypto/md5.h>
14 #include <crypto/sha1.h>
15 #include <crypto/sha2.h>
17 #include <linux/dma-mapping.h>
26 static inline void
31 unsigned int len = req->nbytes + creq->cache_ptr; in mv_cesa_ahash_req_iter_init()
33 if (!creq->last_req) in mv_cesa_ahash_req_iter_init()
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/linux-6.14.4/drivers/soc/qcom/
Dice.c1 // SPDX-License-Identifier: GPL-2.0
3 * Qualcomm ICE (Inline Crypto Engine) support.
5 * Copyright (c) 2013-2019, The Linux Foundation. All rights reserved.
31 /* BIST ("built-in self-test") status flags */
38 #define qcom_ice_writel(engine, val, reg) \ argument
39 writel((val), (engine)->base + (reg))
41 #define qcom_ice_readl(engine, reg) \ argument
42 readl((engine)->base + (reg))
54 struct device *dev = ice->dev; in qcom_ice_check_supported()
66 dev_info(dev, "Found QC Inline Crypto Engine (ICE) v%d.%d.%d\n", in qcom_ice_check_supported()
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/linux-6.14.4/drivers/crypto/caam/
Dintern.h1 /* SPDX-License-Identifier: GPL-2.0 */
6 * Copyright 2008-2011 Freescale Semiconductor, Inc.
14 #include <crypto/engine.h>
16 /* Currently comes from Kconfig param as a ^2 (driver-required) */
20 * Maximum size for crypto-engine software queue based on Job Ring
21 * size (JOBR_DEPTH) and a THRESHOLD (reserved for the non-crypto-API
22 * requests that are not passed through crypto-engine)
25 #define CRYPTO_ENGINE_MAX_QLEN (JOBR_DEPTH - THRESHOLD)
39 * Storage for tracking each in-process entry moving across a ring
60 /* Private sub-storage for a single JobR */
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/linux-6.14.4/drivers/crypto/intel/keembay/
Dkeembay-ocs-ecc.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * Intel Keem Bay OCS ECC Crypto Driver.
5 * Copyright (C) 2019-2021 Intel Corporation
10 #include <crypto/ecc_curve.h>
11 #include <crypto/ecdh.h>
12 #include <crypto/engine.h>
13 #include <crypto/internal/ecc.h>
14 #include <crypto/internal/kpp.h>
15 #include <crypto/kpp.h>
16 #include <crypto/rng.h>
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Docs-aes.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Intel Keem Bay OCS AES Crypto Driver.
5 * Copyright (C) 2018-2020 Intel Corporation
11 #include <linux/dma-mapping.h>
35 * struct ocs_aes_dev - AES device context.
43 * @engine: Crypto engine for the device.
52 struct crypto_engine *engine; member
56 * struct ocs_dll_desc - Descriptor of an OCS DMA Linked List.
81 * ocs_aes_bypass_op() - Use OCS DMA to copy data.
88 static inline int ocs_aes_bypass_op(struct ocs_aes_dev *aes_dev, in ocs_aes_bypass_op()
/linux-6.14.4/drivers/crypto/ccp/
Dccp-crypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * AMD Cryptographic Coprocessor (CCP) crypto API support
16 #include <crypto/algapi.h>
17 #include <crypto/aes.h>
18 #include <crypto/internal/aead.h>
19 #include <crypto/aead.h>
20 #include <crypto/ctr.h>
21 #include <crypto/hash.h>
22 #include <crypto/sha1.h>
23 #include <crypto/sha2.h>
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Dccp-crypto-rsa.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * AMD Cryptographic Coprocessor (CCP) RSA crypto API support
13 #include <linux/crypto.h>
14 #include <crypto/algapi.h>
15 #include <crypto/internal/rsa.h>
16 #include <crypto/internal/akcipher.h>
17 #include <crypto/akcipher.h>
18 #include <crypto/scatterwalk.h>
20 #include "ccp-crypto.h"
22 static inline struct akcipher_request *akcipher_request_cast( in akcipher_request_cast()
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/linux-6.14.4/drivers/crypto/allwinner/sun8i-ce/
Dsun8i-ce.h1 /* SPDX-License-Identifier: GPL-2.0 */
3 * sun8i-ce.h - hardware cryptographic offloader for
6 * Copyright (C) 2016-2019 Corentin LABBE <[email protected]>
8 #include <crypto/aes.h>
9 #include <crypto/des.h>
10 #include <crypto/engine.h>
11 #include <crypto/skcipher.h>
14 #include <linux/crypto.h>
16 #include <crypto/internal/hash.h>
17 #include <crypto/md5.h>
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/linux-6.14.4/drivers/crypto/virtio/
Dvirtio_crypto_common.h1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /* Common header for Virtio crypto device.
11 #include <linux/crypto.h>
14 #include <crypto/aead.h>
15 #include <crypto/aes.h>
16 #include <crypto/engine.h>
31 struct crypto_engine *engine; member
130 struct crypto_engine *engine, void *vreq);
135 static inline int virtio_crypto_get_current_node(void) in virtio_crypto_get_current_node()
/linux-6.14.4/include/crypto/
Dpcrypt.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * pcrypt - Parallel crypto engine.
13 #include <linux/crypto.h>
22 static inline void *pcrypt_request_ctx(struct pcrypt_request *req) in pcrypt_request_ctx()
24 return req->__ctx; in pcrypt_request_ctx()
27 static inline
30 return &req->padata; in pcrypt_request_padata()
33 static inline
/linux-6.14.4/drivers/crypto/tegra/
Dtegra-se.h1 /* SPDX-License-Identifier: GPL-2.0-only
2 * SPDX-FileCopyrightText: Copyright (c) 2023 NVIDIA CORPORATION & AFFILIATES. All rights reserved.
4 * Header file for NVIDIA Security Engine driver.
13 #include <crypto/aead.h>
14 #include <crypto/engine.h>
15 #include <crypto/hash.h>
16 #include <crypto/sha1.h>
17 #include <crypto/sha3.h>
18 #include <crypto/skcipher.h>
155 /* AES Crypto Configuration */
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/linux-6.14.4/drivers/mmc/host/
Dcqhci-crypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * CQHCI crypto engine (inline encryption) support
20 * Returns the crypto bits that should be set in bits 64-127 of the
23 static inline u64 cqhci_crypto_prep_task_desc(struct mmc_request *mrq) in cqhci_crypto_prep_task_desc()
25 if (!mrq->crypto_ctx) in cqhci_crypto_prep_task_desc()
28 /* We set max_dun_bytes_supported=4, so all DUNs should be 32-bit. */ in cqhci_crypto_prep_task_desc()
29 WARN_ON_ONCE(mrq->crypto_ctx->bc_dun[0] > U32_MAX); in cqhci_crypto_prep_task_desc()
32 CQHCI_CRYPTO_KEYSLOT(mrq->crypto_key_slot) | in cqhci_crypto_prep_task_desc()
33 mrq->crypto_ctx->bc_dun[0]; in cqhci_crypto_prep_task_desc()
38 static inline int cqhci_crypto_init(struct cqhci_host *host) in cqhci_crypto_init()
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Dcqhci-crypto.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * CQHCI crypto engine (inline encryption) support
8 #include <linux/blk-crypto.h>
9 #include <linux/blk-crypto-profile.h>
12 #include "cqhci-crypto.h"
14 /* Map from blk-crypto modes to CQHCI crypto algorithm IDs and key sizes */
25 static inline struct cqhci_host *
28 return mmc_from_crypto_profile(profile)->cqe_private; in cqhci_host_from_crypto_profile()
35 u32 slot_offset = cq_host->crypto_cfg_register + slot * sizeof(*cfg); in cqhci_crypto_program_key()
39 cqhci_writel(cq_host, 0, slot_offset + 16 * sizeof(cfg->reg_val[0])); in cqhci_crypto_program_key()
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/linux-6.14.4/Documentation/devicetree/bindings/mmc/
Dsdhci-msm.yaml1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
3 ---
4 $id: http://devicetree.org/schemas/mmc/sdhci-msm.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm SDHCI controller (sdhci-msm)
10 - Bjorn Andersson <[email protected]>
11 - Konrad Dybcio <[email protected]>
20 - enum:
21 - qcom,sdhci-msm-v4
23 - items:
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/linux-6.14.4/drivers/crypto/ccree/
Dcc_driver.h1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2012-2019 ARM Limited (or its affiliates). */
5 * ARM CryptoCell Linux Crypto Driver
16 #include <linux/dma-mapping.h>
17 #include <crypto/algapi.h>
18 #include <crypto/internal/skcipher.h>
19 #include <crypto/aes.h>
20 #include <crypto/sha1.h>
21 #include <crypto/sha2.h>
22 #include <crypto/aead.h>
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/linux-6.14.4/drivers/mmc/core/
Dcrypto.c1 // SPDX-License-Identifier: GPL-2.0-only
3 * MMC crypto engine (inline encryption) support
8 #include <linux/blk-crypto.h>
12 #include "crypto.h"
18 if (host->caps2 & MMC_CAP2_CRYPTO) in mmc_crypto_set_initial_state()
19 blk_crypto_reprogram_all_keys(&host->crypto_profile); in mmc_crypto_set_initial_state()
24 if (host->caps2 & MMC_CAP2_CRYPTO) in mmc_crypto_setup_queue()
25 blk_crypto_register(&host->crypto_profile, q); in mmc_crypto_setup_queue()
32 struct mmc_request *mrq = &mqrq->brq.mrq; in mmc_crypto_prepare_req()
35 if (!req->crypt_ctx) in mmc_crypto_prepare_req()
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Dcrypto.h1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * MMC crypto engine (inline encryption) support
25 static inline void mmc_crypto_set_initial_state(struct mmc_host *host) in mmc_crypto_set_initial_state()
29 static inline void mmc_crypto_setup_queue(struct request_queue *q, in mmc_crypto_setup_queue()
34 static inline void mmc_crypto_prepare_req(struct mmc_queue_req *mqrq) in mmc_crypto_prepare_req()
/linux-6.14.4/drivers/crypto/marvell/octeontx2/
Dotx2_cpt_common.h1 /* SPDX-License-Identifier: GPL-2.0-only
12 #include <linux/crypto.h>
42 /* Take mbox id from end of CPT mbox range in AF (range 0xA00 - 0xBFF) */
49 * Message request to config cpt lf for inline inbound ipsec.
50 * This message is only used between CPT PF <-> CPT VF
67 * Message request and response to get engine group number
83 * Message request and response to get kernel crypto limits
84 * This messages are only used between CPT PF <-> CPT VF
118 * engine type (SE, IE, AE).
132 static inline void otx2_cpt_write64(void __iomem *reg_base, u64 blk, u64 slot, in otx2_cpt_write64()
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/linux-6.14.4/include/linux/
Dccp.h1 /* SPDX-License-Identifier: GPL-2.0-only */
17 #include <crypto/aes.h>
18 #include <crypto/sha1.h>
19 #include <crypto/sha2.h>
27 * ccp_present - check if a CCP device is present
29 * Returns zero if a CCP device is present, -ENODEV otherwise.
34 #define CCP_VMASK ((unsigned int)((1 << CCP_VSIZE) - 1))
39 * ccp_version - get the version of the CCP
46 * ccp_enqueue_cmd - queue an operation for processing by the CCP
55 * result in a return code of -EBUSY.
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/linux-6.14.4/drivers/crypto/
Domap-aes.c1 // SPDX-License-Identifier: GPL-2.0-only
16 #include <crypto/aes.h>
17 #include <crypto/gcm.h>
18 #include <crypto/internal/aead.h>
19 #include <crypto/internal/engine.h>
20 #include <crypto/internal/skcipher.h>
21 #include <linux/dma-mapping.h>
36 #include "omap-crypto.h"
37 #include "omap-aes.h"
49 _read_ret = __raw_readl(dd->io_base + offset); \
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/linux-6.14.4/drivers/crypto/starfive/
Djh7110-aes.c1 // SPDX-License-Identifier: GPL-2.0
8 #include <crypto/engine.h>
9 #include <crypto/gcm.h>
10 #include <crypto/internal/aead.h>
11 #include <crypto/internal/skcipher.h>
12 #include <crypto/scatterwalk.h>
13 #include "jh7110-cryp.h"
52 static inline int starfive_aes_wait_busy(struct starfive_cryp_dev *cryp) in starfive_aes_wait_busy()
56 return readl_relaxed_poll_timeout(cryp->base + STARFIVE_AES_CSR, status, in starfive_aes_wait_busy()
60 static inline int starfive_aes_wait_keydone(struct starfive_cryp_dev *cryp) in starfive_aes_wait_keydone()
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