| /linux-6.14.4/Documentation/devicetree/bindings/display/msm/ |
| D | dsi-controller-main.yaml | 1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
3 ---
4 $id: http://devicetree.org/schemas/display/msm/dsi-controller-main.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Display DSI controller
10 - Krishna Manikandan <[email protected]>
15 - items:
16 - enum:
17 - qcom,apq8064-dsi-ctrl
18 - qcom,msm8226-dsi-ctrl
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| /linux-6.14.4/drivers/gpu/drm/msm/dsi/ |
| D | dsi_manager.c | 1 // SPDX-License-Identifier: GPL-2.0-only
9 #include "dsi.h"
24 struct msm_dsi *dsi[DSI_MAX]; member
39 return msm_dsim_glb.dsi[id]; in dsi_mgr_get_dsi()
44 return msm_dsim_glb.dsi[(id + 1) % DSI_MAX]; in dsi_mgr_get_other_dsi()
51 /* We assume 2 dsi nodes have the same information of bonded dsi and in dsi_mgr_parse_of()
52 * sync-mode, and only one node specifies master in case of bonded mode. in dsi_mgr_parse_of()
54 if (!msm_dsim->is_bonded_dsi) in dsi_mgr_parse_of()
55 msm_dsim->is_bonded_dsi = of_property_read_bool(np, "qcom,dual-dsi-mode"); in dsi_mgr_parse_of()
57 if (msm_dsim->is_bonded_dsi) { in dsi_mgr_parse_of()
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| /linux-6.14.4/drivers/gpu/drm/i915/display/ |
| D | intel_dsi_vbt.c | 69 /* ICL DSI Display GPIO Pins */
85 * If single link DSI is being used on any port, the VBT sequence block in intel_dsi_seq_port_to_port()
89 if (hweight8(intel_dsi->ports) == 1) in intel_dsi_seq_port_to_port()
90 return ffs(intel_dsi->ports) - 1; in intel_dsi_seq_port_to_port()
93 if (intel_dsi->ports & BIT(PORT_B)) in intel_dsi_seq_port_to_port()
95 if (intel_dsi->ports & BIT(PORT_C)) in intel_dsi_seq_port_to_port()
105 struct drm_i915_private *dev_priv = to_i915(intel_dsi->base.base.dev); in mipi_exec_send_packet()
111 drm_dbg_kms(&dev_priv->drm, "\n"); in mipi_exec_send_packet()
123 if (drm_WARN_ON(&dev_priv->drm, !intel_dsi->dsi_hosts[port])) in mipi_exec_send_packet()
126 dsi_device = intel_dsi->dsi_hosts[port]->device; in mipi_exec_send_packet()
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| D | icl_dsi.c | 75 drm_err(display->drm, "DSI header credits not released\n"); in wait_for_header_credits()
87 drm_err(display->drm, "DSI payload credits not released\n"); in wait_for_payload_credits()
106 struct mipi_dsi_device *dsi; in wait_for_cmds_dispatched_to_panel() local
112 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
119 for_each_dsi_port(port, intel_dsi->ports) { in wait_for_cmds_dispatched_to_panel()
120 dsi = intel_dsi->dsi_hosts[port]->device; in wait_for_cmds_dispatched_to_panel()
121 dsi->mode_flags |= MIPI_DSI_MODE_LPM; in wait_for_cmds_dispatched_to_panel()
122 dsi->channel = 0; in wait_for_cmds_dispatched_to_panel()
123 ret = mipi_dsi_dcs_nop(dsi); in wait_for_cmds_dispatched_to_panel()
125 drm_err(display->drm, in wait_for_cmds_dispatched_to_panel()
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| D | vlv_dsi.c | 89 struct intel_display *display = to_intel_display(&intel_dsi->base); in vlv_dsi_wait_for_fifo_empty()
97 drm_err(display->drm, "DPI FIFOs are not empty\n"); in vlv_dsi_wait_for_fifo_empty()
109 for (j = 0; j < min_t(u32, len - i, 4); j++) in write_data()
125 for (j = 0; j < min_t(u32, len - i, 4); j++) in read_data()
134 struct intel_dsi *intel_dsi = intel_dsi_host->intel_dsi; in intel_dsi_host_transfer()
135 struct intel_display *display = to_intel_display(&intel_dsi->base); in intel_dsi_host_transfer()
136 enum port port = intel_dsi_host->port; in intel_dsi_host_transfer()
149 if (msg->flags & MIPI_DSI_MSG_USE_LPM) { in intel_dsi_host_transfer()
165 drm_err(display->drm, in intel_dsi_host_transfer()
172 if (msg->rx_len) { in intel_dsi_host_transfer()
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| D | intel_display.c | 2 * Copyright © 2006-2007 Intel Corporation
27 #include <linux/dma-resv.h>
161 drm_WARN(&dev_priv->drm, (val & CCK_FREQUENCY_STATUS) != in vlv_get_cck_clock()
175 if (dev_priv->hpll_freq == 0) in vlv_get_cck_clock_hpll()
176 dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv); in vlv_get_cck_clock_hpll()
178 hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq); in vlv_get_cck_clock_hpll()
190 dev_priv->czclk_freq = vlv_get_cck_clock_hpll(dev_priv, "czclk", in intel_update_czclk()
193 drm_dbg(&dev_priv->drm, "CZ clock rate: %d kHz\n", in intel_update_czclk()
194 dev_priv->czclk_freq); in intel_update_czclk()
199 return (crtc_state->active_planes & in is_hdr_mode()
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| D | intel_ddi.c | 101 level = intel_bios_hdmi_level_shift(encoder->devdata); in intel_ddi_hdmi_level()
103 level = trans->hdmi_default_entry; in intel_ddi_hdmi_level()
126 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_dp_ddi_buffers()
129 enum port port = encoder->port; in hsw_prepare_dp_ddi_buffers()
132 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); in hsw_prepare_dp_ddi_buffers()
133 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) in hsw_prepare_dp_ddi_buffers()
138 intel_bios_dp_boost_level(encoder->devdata)) in hsw_prepare_dp_ddi_buffers()
143 trans->entries[i].hsw.trans1 | iboost_bit); in hsw_prepare_dp_ddi_buffers()
145 trans->entries[i].hsw.trans2); in hsw_prepare_dp_ddi_buffers()
157 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); in hsw_prepare_hdmi_ddi_buffers()
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| /linux-6.14.4/drivers/gpu/drm/bridge/ |
| D | ti-sn65dsi83.c | 1 // SPDX-License-Identifier: GPL-2.0
6 * - SN65DSI83
7 * = 1x Single-link DSI ~ 1x Single-link LVDS
8 * - Supported
9 * - Single-link LVDS mode tested
10 * - SN65DSI84
11 * = 1x Single-link DSI ~ 2x Single-link or 1x Dual-link LVDS
12 * - Supported
13 * - Dual-link LVDS mode tested
14 * - 2x Single-link LVDS mode unsupported
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| /linux-6.14.4/arch/arm64/boot/dts/qcom/ |
| D | sm8250-xiaomi-elish-common.dtsi | 1 // SPDX-License-Identifier: BSD-3-Clause
3 * Copyright (c) 2022-2024 Jianhua Lu <[email protected]>
6 #include <dt-bindings/arm/qcom,ids.h>
7 #include <dt-bindings/phy/phy.h>
8 #include <dt-bindings/regulator/qcom,rpmh-regulator.h>
9 #include <dt-bindings/usb/pd.h>
20 /delete-node/ &adsp_mem;
21 /delete-node/ &cdsp_secure_heap;
22 /delete-node/ &slpi_mem;
23 /delete-node/ &spss_mem;
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| /linux-6.14.4/drivers/gpu/drm/tegra/ |
| D | dsi.c | 1 // SPDX-License-Identifier: GPL-2.0-only
29 #include "dsi.h"
30 #include "mipi-phy.h"
81 /* for ganged-mode support */
102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi) in tegra_dsi_get_state() argument
104 return to_dsi_state(dsi->output.connector.state); in tegra_dsi_get_state()
107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset) in tegra_dsi_readl() argument
109 u32 value = readl(dsi->regs + (offset << 2)); in tegra_dsi_readl()
111 trace_dsi_readl(dsi->dev, offset, value); in tegra_dsi_readl()
116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value, in tegra_dsi_writel() argument
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| /linux-6.14.4/drivers/gpu/drm/msm/disp/mdp5/ |
| D | mdp5_ctl.c | 1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015 The Linux Foundation. All rights reserved.
10 * CTL - MDP Control Pool Manager
16 * a specific data path ID - REG_MDP5_CTL_*(<id>, ...)
20 * In certain use cases (high-resolution dual pipe), one single CTL can be
62 /* to filter out non-present bits in the current hardware config */
77 struct msm_drm_private *priv = ctl_mgr->dev->dev_private; in get_kms()
79 return to_mdp5_kms(to_mdp_kms(priv->kms)); in get_kms()
85 struct mdp5_kms *mdp5_kms = get_kms(ctl->ctlm); in ctl_write()
87 (void)ctl->reg_offset; /* TODO use this instead of mdp5_write */ in ctl_write()
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| /linux-6.14.4/drivers/gpu/drm/msm/disp/dpu1/ |
| D | dpu_encoder_phys_vid.c | 1 // SPDX-License-Identifier: GPL-2.0-only
2 /* Copyright (c) 2015-2018, 2020-2021 The Linux Foundation. All rights reserved.
18 (e) && (e)->parent ? \
19 (e)->parent->base.id : -1, \
20 (e) && (e)->hw_intf ? \
21 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
24 (e) && (e)->parent ? \
25 (e)->parent->base.id : -1, \
26 (e) && (e)->hw_intf ? \
27 (e)->hw_intf->idx - INTF_0 : -1, ##__VA_ARGS__)
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| /linux-6.14.4/include/drm/ |
| D | drm_connector.h | 58 DRM_FORCE_ON_DIGITAL, /* for DVI-I use digital connector */
62 * enum drm_connector_status - status for a &drm_connector
77 * nothing there. It is driver-dependent whether a connector with this
84 * flicker (like load-detection when the connector is in use), or when a
85 * hardware resource isn't available (like when load-detection needs a
95 * enum drm_connector_registration_state - userspace registration status for
128 * - An unregistered connector may only have its DPMS changed from
129 * On->Off. Once DPMS is changed to Off, it may not be switched back
131 * - Modesets are not allowed on unregistered connectors, unless they
135 * - Removing a CRTC from an unregistered connector is OK, but new
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| /linux-6.14.4/drivers/soc/tegra/ |
| D | pmc.c | 1 // SPDX-License-Identifier: GPL-2.0-only
6 * Copyright (c) 2018-2024, NVIDIA CORPORATION. All rights reserved.
12 #define pr_fmt(fmt) "tegra-pmc: " fmt
14 #include <linux/arm-smccc.h>
16 #include <linux/clk-provider.h>
18 #include <linux/clk/clk-conf.h>
37 #include <linux/pinctrl/pinconf-generic.h>
56 #include <dt-bindings/interrupt-controller/arm-gic.h>
57 #include <dt-bindings/pinctrl/pinctrl-tegra-io-pad.h>
58 #include <dt-bindings/gpio/tegra186-gpio.h>
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| /linux-6.14.4/drivers/gpu/drm/stm/ |
| D | ltdc.c | 1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/media-bus-format.h>
46 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
61 #define LAY_OFS (ldev->caps.layer_ofs)
87 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */
88 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */
89 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */
90 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */
91 #define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */
92 #define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */
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| /linux-6.14.4/ |
| D | CREDITS | 1 This is at least a partial credits-file of people that have
4 scripts. The fields are: name (N), email (E), web-address
6 snail-mail address (S).
10 ----------
51 D: in-kernel DRM Maintainer
76 E: tim_alpaerts@toyota-motor-europe.com
80 S: B-2610 Wilrijk-Antwerpen
85 W: http://www-stu.christs.cam.ac.uk/~aia21/
106 D: Maintainer of ide-cd and Uniform CD-ROM driver,
107 D: ATAPI CD-Changer support, Major 2.1.x CD-ROM update.
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| D | MAINTAINERS | 5 ---------------------------------------------------
21 W: *Web-page* with status/info
23 B: URI for where to file *bugs*. A web-page with detailed bug
28 patches to the given subsystem. This is either an in-tree file,
29 or a URI. See Documentation/maintainer/maintainer-entry-profile.rst
46 N: [^a-z]tegra all files whose path contains tegra
64 ----------------
83 3WARE SAS/SATA-RAID SCSI DRIVERS (3W-XXXX, 3W-9XXX, 3W-SAS)
85 L: linux-[email protected]
88 F: drivers/scsi/3w-*
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